3. Introduction
The CMS Silicon Strip Tracker (SST) will
instrument the central region of the CMS
experiment. It will be composed of four parts:
Tracker Inner Barrel (TIB)
Tracker Outer Barrel (TOB)
Two Tracker End Caps (TEC).
The SST provides the reconstruction of the
tracks of particles, which are created by the
collision of high energy protons (7 TeV each)
in the planned accelerator LHC.
6. Detectors
About 16000 silicon micro strip detector modules are
foreseen to equip the SST constructing the largest all-
silicon tracker in the world.
One individual silicon detector module essentially consists
of three elements, a set of silicon sensors, a mechanical
support structure and the front end electronics (FE
hybrid).
8. Introduction to ARC
The test facility which will be introduced here
is intended for diagnostic testing and quality
assurance of FE hybrids and silicon detector
modules.
The concept provides a very compact and
flexible structure.
This low cost test setup evolving in Aachen is
called APV Readout Controller ARC.
9. Introduction to ARCS
While ARC provides complete control of
the hybrid and all its ASIC chips.
An individually designed LabVIEW
application called APV Readout
Controller Software (ARCS) serves as a
userfriendly graphical user interface
which allows an easy implementation of
automatic test procedures.
10. ARC System Overview
A fully assebled ARC
systems is composed of:
APV Redaut Controller
PCMIO Interfaces
ARC Board Frontend
Adapter
HV Board (DEPP)
ARCS software
12. APV Readout Controller
The ARC Board is the central device of the
ARC System.
It provides full operational control of
connected Frontend (FE) hybrids.
There are three main function blocks on the
ARC board for the operation of FE hybrids:
clock and trigger, data sampling and I²C
communication (slow control / low voltage
control).
The ARC board fits into a standard 19inch
crate.
16. CLOCK AND TRIGGER
The clock is primary generated by a local crystal oscillator.
A software or an external ( NIM ) generated asynchron
trigger is latched and then synchronised with the system
clock.
Awaked by this synchronised trigger an APV trigger pattern is
sent to each front end hybrid.
The trigger pattern has to be loaded into a local 16 bit data
register.
The MSB will be send first to the APV’s. Any possible APV
trigger pattern ( RESET, CAL REQUEST, EVENT TRIGGER )
has to be generated via this way.
The trigger signal is distributed by a separate trigger link or if
selected ( status register D7 ) as clock missing pulses.
17. DATA SAMPLING
Two groups of three eight bit FADC’s (one group for each
hybrid ) sample the analogue data with a synchronised 40
or 20 MHz clock (selected by status register D8 ).
For correct sample timing the FADC clock phase should be
tuned, in ten steps of ~ 1.7 ns (ADC Clock Delay register ).
The digitised data are stored in an 8 Kbyte RAM for each
channel.
The sample record length is determined by the stop
address.
Sampling starts at address 0 and stops at the defined stop
address ( stop address register ).
18. DATA SAMPLING
The stop address may be set to any value between
0 and 8 Kbyte.
A record complete is flagged in bit D1 of status
register.
A PC program may read this flag in polling mode
and read the data after this bit is set.
Before data read, the memory address counter
should be set to the favorite start address (memory
address register ), a read cycle increments the
address counter automatically.
19. SLOW CONTROL and LOW
VOLTAGE CONTROL
There are three I_C controllers [11] located on
the ARC board.
Two of them are used for hybrid slow
controlpurposes (one controller for each hybrid)
providing the communication between the PC and
the ASICs.
The third controller allows control and monitoring
of the hybrid low voltage power consumption.
The low voltage regulators are mounted on the
FE adapter which can be controlled via the ARC
board.
20. PCMIO INTERFACE
The PCMIO card fits into an ISA slot and
serves as interface between the ISA bus and
the ARC board.
Alternatively it is possible to use the PC LPT
port as an interface to connect ARC to the
PC.
It is mandatory that the LPT port provides the
standard Enhanced Parallel Port protocol.
An external EPP Interface allows using a
notebook as control computer resulting in a
fully portable system.
22. Functional description
The module is an ISA_Bus-Extender with an
address rangee of 64 words (A6..A0).
The 16 data-lines (D15..D0), 6 address-lines
(A6..A1) andd three controll-lines from the
ISA bus are buffered and linked via a 50 pin
connector/cable to the SRDPC-bus.
Power consumption 390mA @5VDC
23. ARC Board Frontend Adapter
The ARC FE adapter card
consists of two printed
circuit boards
(dimensions: 72mm _
72mm) stacked onto each
other.
The hybrid isconnected to
the ARC FE adapter which
is directly connected to
the ARC board via one 26
pin twisted pair flat cable.
24. ARC Board Frontend Adapter
Three function groups are housed on
the first printed circuit board:
An I _C level shifter which serves as a
bidirectional FET shifter
Three differential input and differential
output buffers are used for analogue data
buffering
Clock and trigger function group.
25. ARC Board Frontend Adapter
The second board houses the voltage
regulation circuit for the hybrid low voltage.
The separation of the high power dissipating
part from the FE adapter facilitates the use of
the ARC system for hybrid and module thermal
cycling tests.
Only the level shifter and the analogue buffer
need to be close to the hybrid while the high
power part can be located away from the
hybrid.
26. ARC Board Frontend Adapter:
Ibrid power regulation
Is designed as a voltage tracking regulator to avoid reverse
currents due to failures on a hybrid, i.e. V125 is always half
of V250.
The capability of controlling hybrid currents and voltages if
avaible on the two power lines via the I2C interface.
The voltages can be adjusted within a range of +4%/-15%
compared to the nominal oltages.
Safety concerning hybrid power consumption is guaranteed
by an overvoltage protection and a current limiter.
Hybrid voltages and the corresponding currents are read
out by software and displayed on the monitor screen.
27. HV Board (DEPP)
The High Voltage Board (DEPP) is designed to
supply silicon detector modules with a voltage in a
range of 0 to 600 Volts (resolution: 150 mV /
count).
It also provides the measurement of the
detectors´ leakage current in the range of 20 µA
(resolution: 5nA / count).
The HV Board is connected to the ISA Bus and
therefore easily controllable via the ARC
Software.
The DEPP was designed to be plugged into a
19inch crate.
29. ARC Software
This software application is called APV
Readout Controller Software (ARCS)
and was developed using LabVIEW 6i.
The direct communication between ARC
and the application is based on dynamic
link libraries or shared libraries written
in C/C++ language embedded in the
LabVIEW code.
30. The current status of ARCS
Monitoring and storage of FE hybrid data
After a proper initialisation phase (writing and reading
the chip parameters) of the ARC board itself and the I _C
controller (including an I_C address scan), it is possible to
communicate with the chips.
The subsequent phase includes the monitoring of hybrid
data where the display of APV frames and the hybrid
currents and voltages are enabled.
The online monitoring of the APV data (ordered or
unordered data, raw data, pedestal corrected data)
delivers first indications of the functionality of the tested
FE electronics.
Additionally raw data or pedestals, rms noise and gain
can be written to disc or to the database enabling
detailed offline analysis.
31. The current status of ARCS
Automated Fast Tests
Is intended for industry purposes: Based on
experiences gained with one preprototype FE
hybrid (see below), a table of selectable tests
is provided in ARCS. These tests will be
executed automatically.
A passed test is indicated by a green and a
failed test by a red light. All results are
written into ASCII files.
33. LED Pulser (LEP16)
The LED Pulser (LEP 16) is
a PCB providing single and
parallel operation and
control of maximum 16
LEDs via the ARC Software.
For each LED the
pulslength (0-15 x 25ns)
and intensity can be
modified.
The LED Pulser was
designed to be plugged into
a 19inch crate.
