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VERILOG CODE

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VERILOG CODE FOR 32-BIT BARREL SHIFTER,32-BIT ADDER AND MANY MORE...

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VERILOG CODE

  1. 1. CA ASSIGNMENT-6 BY KANERIA DHAVAL BARREL SHIFTER module barrel ( input [n:0]in, input [4:0]sh, input shift_LeftRight,rotate_LeftRight, output reg [n:0] out); parameter n=31; always@* begin if(~shift_LeftRight) out = in<<sh; else if(shift_LeftRight) out = in>>sh; else begin case(sh) 5'b00001: out=(~rotate_LeftRight)?{in[n-1:0],in[n]}:{in[0],in[n:1]}; 5'b00010: out=(~rotate_LeftRight)?{in[n-2:0],in[n:n-1]}:{in[1:0],in[n:2]}; 5'b00011: out=(~rotate_LeftRight)?{in[n-3:0],in[n:n-2]}:{in[2:0],in[n:3]};
  2. 2. 5'b00100: out=(~rotate_LeftRight)?{in[n-4:0],in[n:n-3]}:{in[3:0],in[n:4]}; 5'b00101: out=(~rotate_LeftRight)?{in[n-5:0],in[n:n-4]}:{in[4:0],in[n:5]}; 5'b00110: out=(~rotate_LeftRight)?{in[n-6:0],in[n:n-5]}:{in[5:0],in[n:6]}; 5'b00111: out=(~rotate_LeftRight)?{in[n-7:0],in[n:n-6]}:{in[6:0],in[n:7]}; 5'b01000: out=(~rotate_LeftRight)?{in[n-8:0],in[n:n-7]}:{in[7:0],in[n:8]}; 5'b01001: out=(~rotate_LeftRight)?{in[n-9:0],in[n:n-8]}:{in[8:0],in[n:9]}; 5'b01010: out=(~rotate_LeftRight)?{in[n-10:0],in[n:n-9]}:{in[9:0],in[n:10]}; 5'b01011: out=(~rotate_LeftRight)?{in[n-11:0],in[n:n-10]}:{in[10:0],in[n:11]}; 5'b01100: out=(~rotate_LeftRight)?{in[n-12:0],in[n:n-11]}:{in[11:0],in[n:12]}; 5'b01101: out=(~rotate_LeftRight)?{in[n-13:0],in[n:n-12]}:{in[12:0],in[n:13]}; 5'b01110: out=(~rotate_LeftRight)?{in[n-14:0],in[n:n-13]}:{in[13:0],in[n:14]}; 5'b01111: out=(~rotate_LeftRight)?{in[n-15:0],in[n:n-14]}:{in[14:0],in[n:15]}; 5'b10000: out=(~rotate_LeftRight)?{in[n-16:0],in[n:n-15]}:{in[15:0],in[n:16]}; 5'b10001: out=(~rotate_LeftRight)?{in[n-17:0],in[n:n-16]}:{in[16:0],in[n:17]}; 5'b10010:
  3. 3. out=(~rotate_LeftRight)?{in[n-18:0],in[n:n-17]}:{in[17:0],in[n:18]}; 5'b10011: out=(~rotate_LeftRight)?{in[n-19:0],in[n:n-18]}:{in[18:0],in[n:19]}; 5'b10100: out=(~rotate_LeftRight)?{in[n-20:0],in[n:n-19]}:{in[19:0],in[n:20]}; 5'b10101: out=(~rotate_LeftRight)?{in[n-21:0],in[n:n-20]}:{in[20:0],in[n:21]}; 5'b10110: out=(~rotate_LeftRight)?{in[n-22:0],in[n:n-21]}:{in[21:0],in[n:22]}; 5'b10111: out=(~rotate_LeftRight)?{in[n-23:0],in[n:n-22]}:{in[22:0],in[n:23]}; 5'b11000: out=(~rotate_LeftRight)?{in[n-24:0],in[n:n-23]}:{in[23:0],in[n:24]}; 5'b11001: out=(~rotate_LeftRight)?{in[n-25:0],in[n:n-24]}:{in[24:0],in[n:25]}; 5'b11010: out=(~rotate_LeftRight)?{in[n-26:0],in[n:n-25]}:{in[25:0],in[n:26]}; 5'b11011: out=(~rotate_LeftRight)?{in[n-27:0],in[n:n-26]}:{in[26:0],in[n:27]}; 5'b11100: out=(~rotate_LeftRight)?{in[n-28:0],in[n:n-27]}:{in[27:0],in[n:28]}; 5'b11101: out=(~rotate_LeftRight)?{in[n-29:0],in[n:n-28]}:{in[28:0],in[n:29]}; 5'b11110: out=(~rotate_LeftRight)?{in[n-30:0],in[n:n-29]}:{in[29:0],in[n:30]}; 5'b11111: out=(~rotate_LeftRight)?{in[n-31:0],in[n:n-30]}:{in[30:0],in[n:31]}; default:
  4. 4. out=in; endcase end end endmodule `timescale 1ns / 1ps module barrel_tb #(parameter n=31)(); reg [n:0]in; reg [5:0]sh; reg shift_LeftRight,rotate_LeftRight; wire [n:0] out; barrel bs(.in(in),.sh(sh),.shift_LeftRight(shift_LeftRight),.rotate_LeftRight(rotate_LeftRight),.out(out)); initial begin #1 in=32'b11111111111111110000000000000000;sh=5'b00000;rotate_LeftRight=1'b1;shift_LeftRight=1'bx ; #1 sh=5'b00001; #1 sh=5'b00010; #1 sh=5'b00011; #1 sh=5'b00100; #1 sh=5'b00101; #1 sh=5'b00110; #1 sh=5'b00111;
  5. 5. #1 sh=5'b00000;in=32'b11111111111111110000000000000000;rotate_LeftRight=1'b0; #1 sh=5'b00001; #1 sh=5'b00010; #1 sh=5'b00011; #1 sh=5'b00100; #1 sh=5'b00101; #1 sh=5'b00110; #1 sh=5'b00000;in=32'b11111111111111110000000000000000;rotate_LeftRight=1'bx;shift_LeftRight=1'b0 ; #1 sh=5'b00001; #1 sh=5'b00010; #1 sh=5'b00011; #1 sh=5'b00100; #1 sh=5'b00101; #1 sh=5'b00110; #1 sh=5'b00000;in=32'b11111111111111110000000000000000;shift_LeftRight=1'b1; #1 sh=5'b00001; #1 sh=5'b00010; #1 sh=5'b00011; #1 sh=5'b00100; #1 sh=5'b00101; #1 sh=5'b00110; end
  6. 6. initial #32 $finish; initial begin // Initialize Inputs in = 0; sh = 0; shift_LeftRight = 0; rotate_LeftRight = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule
  7. 7. 8 BIT BOOTH MULTIPLIER module multiplier(prod, busy, mc, mp, clk, start); output [15:0] prod; output busy; input [7:0] mc, mp; input clk, start; reg [7:0] A, Q, M; reg Q_1; reg [7:0] count; wire [7:0] sum, difference;
  8. 8. always @(posedge clk) begin if (start) begin A <= 8'b0; M <= mc; Q <= mp; Q_1 <= 1'b0; count <= 7'b0; end else begin case ({Q[0], Q_1}) 2'b01 : {A, Q, Q_1} <= {sum[7], sum, Q}; 2'b10 : {A, Q, Q_1} <= {difference[7], difference, Q}; default: {A, Q, Q_1} <= {A[7], A, Q}; endcase count <= count + 1'b1; end end alu adder (sum, A, M, 1'b0); alu subtracter (difference, A, ~M, 1'b1); assign prod = {A, Q}; assign busy = (count < 8); endmodule //The following is an alu.
  9. 9. //It is an adder, but capable of subtraction: //Recall that subtraction means adding the two's complement-//a - b = a + (-b) = a + (inverted b + 1) //The 1 will be coming in as cin (carry-in) module alu(out, a, b, cin); output [7:0] out; input [7:0] a; input [7:0] b; input cin; assign out = a + b + cin; endmodule TEST BENCH module boothm_tb; // Inputs reg [7:0] mc; reg [7:0] mp; reg clk; reg start; // Outputs wire [15:0] prod; wire busy; // Instantiate the Unit Under Test (UUT)
  10. 10. multiplier uut ( .prod(prod), .busy(busy), .mc(mc), .mp(mp), .clk(clk), .start(start) ); initial begin // Initialize Inputs mc = 0; mp = 0; clk =0; // start = 1; // Wait 100 ns for global reset to finish // Add stimulus here #5 mc = 5; mp = 3; start = 1; #5 start = 0; //#5 mc = 5; mp = 3; start = 1; //#5 start = 0; #80 $finish; end always #5 clk = ~clk;
  11. 11. endmodule 32 BIT FULL ADDER(CARRY RIPPLE ADDER) module fulladder_32bit( input [7:0] a0, input [7:0] a1, input [7:0] a2,
  12. 12. input [7:0] a3, input [7:0] b0, input [7:0] b1, input [7:0] b2, input [7:0] b3, output [7:0] s0, output [7:0] s1, output [7:0] s2, output [7:0] s3, output cout, input cin ); wire w1,w2,w3; adder_8bit a(a0,b0,cin,s0,w1); adder_8bit b(a1,b1,w1,s1,w2); adder_8bit c(a2,b2,w2,s2,w3); adder_8bit d(a3,b3,w3,s3,cout); endmodule SUB MODULE(8 BIT FULLADDER) module adder_8bit( input [7:0] a, input [7:0] b, input cin, output reg [7:0] sum, output reg cout
  13. 13. ); always @(a,b,cin) {cout,sum} = a+b+cin; Endmodule TEST BENCH module fulladder; // Inputs reg [7:0] a0; reg [7:0] a1; reg [7:0] a2; reg [7:0] a3; reg [7:0] b0; reg [7:0] b1; reg [7:0] b2; reg [7:0] b3; reg cin; // Outputs wire [7:0] s0; wire [7:0] s1; wire [7:0] s2; wire [7:0] s3; wire cout; // Instantiate the Unit Under Test (UUT)
  14. 14. fulladder_32bit uut ( .a0(a0), .a1(a1), .a2(a2), .a3(a3), .b0(b0), .b1(b1), .b2(b2), .b3(b3), .s0(s0), .s1(s1), .s2(s2), .s3(s3), .cout(cout), .cin(cin) ); initial begin // Initialize Inputs a0 = 0; a1 = 0; a2 = 0; a3 = 0; b0 = 0; b1 = 0; b2 = 0; b3 = 0; cin = 0;
  15. 15. // Wait 100 ns for global reset to finish #100; #200 a0=8'h66; a1=8'h66; a2=8'h66; a3=8'h66; b0=8'hAA; b1=8'hAA; b2=8'hAA; b3=8'hAA; #200 a0=8'h55; a1=8'h55; a2=8'h55; a3=8'h55; b0=8'h55; b1=8'h55; b2=8'h55; b3=8'h55; #200 a0=8'h00; a1=8'h00; a2=8'h00; a3=8'h00; b0=8'hAA; b1=8'hAA; b2=8'hAA; b3=8'hAA; #200 a0=8'h55; a1=8'h55; a2=8'h55; a3=8'h55; b0=8'hF3; b1=8'h22; b2=8'h4C; b3=8'hB5; // Add stimulus here end endmodule
  16. 16. 32 SIMPLE(DIRECT) ADDER module adder_32bit( input [31:0] a, input [31:0] b, input cin, output reg [31:0] sum, output reg cout ); always @(a,b,cin) {cout,sum} = a+b+cin; Endmodule TEST BENCH module adder32bit; // Inputs reg [31:0] a; reg [31:0] b; reg cin; // Outputs wire [31:0] sum; wire cout;
  17. 17. // Instantiate the Unit Under Test (UUT) adder_32bit uut ( .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout) ); initial begin // Initialize Inputs a = 0; b = 0; cin = 0; // Wait 100 ns for global reset to finish #100; #200 a=32'h66666666; b=32'h55555555; #200 a=32'h00000000; b=32'h11111111; #200 a=32'h98765432; b=32'hAAAAAAAA; #200 a=32'h12121212; b=32'h21212121; #200 a=32'h12345678; b=32'hF0000000; // Add stimulus here end endmodule
  18. 18. 32 BIT CARRY LOOKAHED ADDER module FORWARD_32BIT( input [7:0] a0, input [7:0] a1, input [7:0] a2, input [7:0] a3, input [7:0] b0, input [7:0] b1, input [7:0] b2, input [7:0] b3, input cin, output [7:0] s0, output [7:0] s1, output [7:0] s2, output [7:0] s3, output cout );
  19. 19. wire w1,w2,w3; fulladd4 a(s0,w1,a0,b0,cin); fulladd4 b(s1,w2,a1,b1,w1); fulladd4 c(s2,w3,a2,b2,w2); fulladd4 d(s3,cout,a3,b3,w3); endmodule TEST BENCH module forward_32bit_tb; // Inputs reg [7:0] a0; reg [7:0] a1; reg [7:0] a2; reg [7:0] a3; reg [7:0] b0; reg [7:0] b1; reg [7:0] b2; reg [7:0] b3; reg cin; // Outputs wire [7:0] s0; wire [7:0] s1; wire [7:0] s2;
  20. 20. wire [7:0] s3; wire cout; // Instantiate the Unit Under Test (UUT) FORWARD_32BIT uut ( .a0(a0), .a1(a1), .a2(a2), .a3(a3), .b0(b0), .b1(b1), .b2(b2), .b3(b3), .cin(cin), .s0(s0), .s1(s1), .s2(s2), .s3(s3), .cout(cout) ); initial begin // Initialize Inputs a0 = 0; a1 = 0; a2 = 0; a3 = 0; b0 = 0; b1 = 0;
  21. 21. b2 = 0; b3 = 0; cin = 0; // Wait 100 ns for global reset to finish #100; #200 a0=8'h00; a1=8'h00; a2=8'h00; a3=8'h00; b0=8'hAA; b1=8'hAA; b2=8'hAA; b3=8'hAA; #200 a0=8'h11; a1=8'h11; a2=8'h11; a3=8'h11; b0=8'h11; b1=8'h11; b2=8'h11; b3=8'h11; #200 a0=8'h00; a1=8'h00; a2=8'h00; a3=8'h00; b0=8'hAA; b1=8'hAA; b2=8'hAA; b3=8'hAA; #200 a0=8'h12; a1=8'h34; a2=8'h56; a3=8'h78; b0=8'h00; b1=8'h00; b2=8'h00; b3=8'h11; end endmodule
  22. 22. PIPELINE PROGRAM FOR GIVEN DIAGRAM module main( input [7:0] a, input [7:0] b, input [7:0] c, input [7:0] d, input [7:0] e, input clk, input rst, output [7:0] out ); wire [7:0] w1,w2,w3,w4,w5,w6,w7,w8; dff d1(a,rst,clk,w1); dff d2(b,rst,clk,w2); mul m1(w1,w2,w3); dff d3(w3,rst,clk,w4); add a1(c,w4,w5); dff d4(w5,rst,clk,w6); sub s1(d,w6,w7); dff d5(w7,rst,clk,w8); shift s2(e,w8,out); endmodule SUB MODULE FOR DFF
  23. 23. module dff( input [7:0] din, input rst, input clk, output reg [7:0] dout ); always @(posedge clk,negedge rst) begin if(!rst) dout = 8'b00000000; else dout = din; end endmodule SUB MODULE FOR MUL module mul( input [7:0] a, input [7:0] b, output reg [7:0] out ); reg [7:0] r1,r2,r3,r4; always @(a,b) begin if(b[0]) r1 = {4'b0000,a};
  24. 24. else r1 = 8'b00000000; if(b[1]) r2 = {3'b000,a,1'b0}; else r2 = 8'b00000000; if(b[2]) r3 = {2'b00,a,2'b00}; else r3 = 8'b00000000; if(b[3]) r4 = {1'b0,a,3'b000}; else r4 = 8'b00000000; out = r1+r2+r3+r4; end endmodule SUBMODULE FOR ADD module add( input [7:0] a, input [7:0] b,
  25. 25. output reg [7:0] out ); always @(a,b) out = a+b; endmodule SUBMODULE FOR SUB module sub( input [7:0] a, input [7:0] b, output reg [7:0] out ); always @(a,b) out = a-b; endmodule SUBMODULE FOR SHIFT module shift( input [7:0] a, input [7:0] b, output reg [7:0] out ); always @(a,b) out = b<<a;
  26. 26. endmodule TESTBENCH module main_tb; // Inputs reg [7:0] a; reg [7:0] b; reg [7:0] c; reg [7:0] d; reg [7:0] e; reg clk; reg rst; wire [7:0] out; // Instantiate the Unit Under Test (UUT) main uut ( .a(a), .b(b), .c(c), .d(d), .e(e), .clk(clk), .rst(rst),
  27. 27. .out(out) ); always #200 clk = ~clk; initial begin // Initialize Inputs a = 0; b = 0; c = 0; d = 0; e = 0; clk = 0; rst = 1; #200 rst = 0; #400 rst = 1; #200 a=8'h01; b=8'h02; c=8'h03; d=8'h04; e=8'h01; #800 a=8'h08; b=8'h03; #800 c=8'h03; #800 d=8'h03; #800 e=8'h04; end endmodule
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VERILOG CODE FOR 32-BIT BARREL SHIFTER,32-BIT ADDER AND MANY MORE...

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