Guy Eschemann

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I'm an electrical engineer with a strong focus on FPGA design. I work mostly with the VHDL hardware description language, using Eclipse and the Sigasi plugin as my development environment. My simulator of choice is Aldec Riviera-PRO. I also develop software in C, Java and Python. My company provides FPGA design services and develops custom electronic design automation (EDA) tools such as code generators. Our latest project is a register interface generator which generates VHDL code, C drivers, and HTML/RTF documentation from a single XML register map specification. The customer, a reputed German company, has already started using it in several safety-critical FPGA projects. To keep myse...

vhdl fpga system-verilog axi4 c eda verilog myhdl python

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Guy Eschemann

Présentations

FPGA Design with Python and MyHDL

airhdl -- A Web-Based Register File Generator for Xilinx ZYNQ, MicroBlaze, and any other AXI4-lite system.

Managing register banks in the cloud with airhdl

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