POWER DISSIPATION

1. Power Dissipation
CMOS

2. Outline
• Motivation to estimate power dissipation
• Sources of power dissipation
• Dynamic power dissipation
• Static power dissipation
• Metrics
• Conclusion

3. Need to estimate power dissipation
Power dissipation affects
• Performance
• Reliability
• Packaging
• Cost
• Portability

4. Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors

5. Node Transition Activity and Power
•Due to charging and discharging of capacitance
Consider switching a CMOS gate for N clock cycles
E
N
=  2  nN
C
L
V
dd
EN : the energy consumed for N clock cycles
n(N): the number o f 0->1 transition in N clock cycles
P
avg
lim
N 
E
N
N
-------- f
clk
= 
nN
N
 lim
------------
  C
 
N 
L
V
dd

2
f
clk
= 
= lim

0  1
nN
------------
N
N  
P
avg
= 
 C
0  1
L
 2 f
V
dd
clk


6. Activity factors of basic gates
• AND
• OR
• XOR
A B A B   (1 p p ) p p
(1 )(1 )[1 (1 )(1 )] A B A B    p  p   p  p
[1 ( 2 )]( 2 ) A B A B A B A B    p  p  p p p  p  p p

7. Dynamic Power dissipation
• Power reduced by reducing Vdd, f, C and also activity
• A signal transition can be classified into two categories
 a functional transition and
 a glitch

8. Glitch Power Dissipation
• Glitches are temporary changes in the value of the output –
unnecessary transitions
• They are caused due to the skew in the input signals to a gate
• Glitch power dissipation accounts for 15% – 20 % of the
global power
• Basic contributes of hazards to power dissipation are
– Hazard generation
– Hazard propagation

9. Glitch Power Dissipation
• P = 1/2 .CL.Vdd . (Vdd – Vmin) ;
Vmin : min voltage swing at the output
• Glitch power dissipation is dependent on
– Output load
– Input pattern
– Input slope

11. Glitch Power Dissipation
• Hazard generation can be reduced by gate sizing and path
balancing techniques
• Hazard propagation can be reduced by using less number of
inverters which tend to amplify and propagate glitches

12. Short Circuit Power Dissipation
• Short circuit current occurs during signal transitions when
both the NMOS and PMOS are ON and there is a direct path
between Vdd and GND
• Also called crowbar current
• Accounts for more than 20% of total power dissipation
• As clock frequency increases transitions increase
consequently short circuit power dissipation increases
• Can be reduced :
– faster input and slower output
– Vdd <= Vtn + |Vtp|
• So both NMOS and PMOS are not on at the same time

14. Static Power Consumption
Vin=5V
Vout
CL
Vdd
Istat
Pstat = P(In=1).Vdd . Istat
• Dominates over dynamic consumption
Wasted energy …
Should be avoided in almost all cases
• Not a function of switching frequency

15. Static Power Dissipation
• Power dissipation occurring when device is in standby mode
• As technology scales this becomes significant
• Leakage power dissipation
• Components:
– Reverse biased p-n junction
– Sub threshold leakage
– DIBL leakage
– Channel punch through
– GIDL Leakage
– Narrow width effect
– Oxide leakage
– Hot carrier tunneling effect

16. Leakage Current

19. New Problem: Gate Leakage
„Now about 20-30% of all leakage, and growing
„Gate oxide is so thin, electrons tunnel thru it…
„NMOS is much worse than PMOS

20. Principles for Power Reduction
• Prime choice: Reduce voltage!
– Recent years have seen an acceleration in
supply voltage reduction
– Design at very low voltages still open question
(0.6 … 0.9 V by 2010!)
• Reduce switching activity
Logic synthesis
Clock gating
• Reduce physical capacitance
– Proper Device Sizing
– Good layout

21. Factors affecting leakage power
• Temperature
– Sub-threshold current increases exponentially
• Reduction in Vt
• Increase in thermal voltage
– BTBT increases due to band gap narrowing
– Gate leakage is insensitive to temperature change

22. Factors affecting leakage power
• Gate oxide thickness
– Sub-threshold current decreases in long channel transistors and
increases in short channel
– BTBT is insensitive
– Gate leakage increases as thickness reduces

23. Solutions
• MTCMOS
• Dual Vt
• Dual Vt domino logic
• Adaptive Body Bias
• Transistor stacking

24. Metrics
• Power Delay product
• Energy Delay Product
– Average energy per instruction x average inter instruction
delay
• Cunit_area
– Capacitance per unit area

25. Summary
„Power Dissipation is already a prime design constraint
„Low-power design requires operation at lowest possible
voltage and clock speed
„Low-power design requires optimization at

26. Conclusion
• Power dissipation is unavoidable especially as technology
scales down
• Techniques must be devised to reduce power dissipation
• Techniques must be devised to accurately estimate the power
dissipation
• Estimation and modeling of the sources of power dissipation
for simulation purposes