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Fan-Out WLP and PLP Technologies 2021 - Sample

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TSMC’s Fan-Out success with Apple and high-performance computing are pushing Intel, Samsung, ASE, and all other competitors to find new innovative solutions.
More information: https://www.i-micronews.com/products/fan-out-wlp-and-plp-applications-and-technologies-2021/

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Fan-Out WLP and PLP Technologies 2021 - Sample

  1. 1. © 2021 From Technologies to Markets Fan-OutWLP and PLP Technologies 2021 Sample Market and Technology Report 2021
  2. 2. 2 • Table of contents 2 • Scope of the report 4 • Report methodology & definitions 5 • About the authors 6 • Yole Group of companies related reports 7 • Glossary 8 • Companies cited in this report 9 • What we got right, what we got wrong 10 • Three-page summary 11 • Executive summary 15 • Context 56 o Scope of Fan-Out Packaging 57 o Fan-Out Packaging definition 60 o Fan-Out Packaging introduction 63 o Fan-Out Packaging segmentation 67 • Market forecasts 76 o Fan-Out Packaging revenue forecasts 77 o Total overview o End-market o Post COVID-19 impact o Core FO vs HD FO vs UHD FO o FOWLP vs FOPLP o Breakdown by carrier type & market segment o Application o Fan-Out Packaging unit forecasts 88 o Total overview o End-market o Production volume, 300mm wafer equivalent o Core FO vs HD FO vs UHD FO Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 TABLE OF CONTENTS Part 1/2 • Market shares 94 o What’s new? 95 o Market shares of manufacturers 97 o Market shares of IC substrate vs Fan-Out technologies 107 o Market shares of Si interposer vs UHD Fan-Out technologies 111 o Market shares of IC substrate vs Fan-Out technologies 114 o Market shares of Business Models 117 o Reason behind TSMC dominance o Chapter conclusion 127 • Supply chain 130 o What’s new? 131 o Supply chain overview 133 o Global mapping 137 o Fan-Out key suppliers activity summary 140 o Fan-Out players: positioning 146 o Overview of players positioning o Deca’s business model transition o Nepes’ Fan-Out packaging company spin-off: Nepes Laweh o Analysis of the latest developments in supply chain 156 o Analysis of key players within respective business models o New supply chain trends: more UHD FO players o Main players of FOPLP vs FOWLP o Chapter conclusion 174
  3. 3. 3 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 TABLE OF CONTENTS Part 2/2 • Market trends 176 o Market drivers 177 o Big die packaging is trending in HPCs 180 o Why is Fan-Out Packaging being adopted for HPC? o APE in mobile devices 191 o Why is Fan-Out Packaging adopted in mobile APE? o Radar is trending in automotive 197 o Why is Fan-Out Packaging being adopted in automotive radar? o Mobile AiP is trending with 5G 208 o Why is Fan-Out Packaging possibly adopted for AiP? o Fan-Out Packaging drivers 218 o Chapter conclusion 230 • Commercialization status 233 o What’s new? 234 o Overview 237 o Commercialization Window: segmented by I/O Count & package size 241 o PMIC 250 o Audio codec 252 o Automotive radar 254 o Smartphones APE 259 o Smartphone AiP 265 o Smartwatches 268 o HPC 272 o Chapter conclusion 285 • Technology trends 287 o What’s new? 288 o Fan-Out Packaging technology roadmaps 290 o Fan-Out Packaging technology by manufacturers 297 o Perspective on technology 350 o Chapter conclusion 354 • Fan-Out Panel Level Packaging 357 o Panel-trends and motivations 358 o FOPLP supply chain 366 o Global map of FOPLP manufacturers o FOPLP manufacturers status o New developments for FOPLP 377 o Reality of panel penetration 381 o Chapter conclusion 386 • Report conclusion 389 • Appendix 392 o Background of Fan-Out players/ technologies 393 o Fan-Out Packaging process flow 412 o Fan-Out drivers: where is the threshold? 420 o Fan-Out Packaging technology by manufacturers 424 o Fan-Out Packaging technical challenges 444 • Yole Corporate presentation 447
  4. 4. 4 The main objectives of this report are: • To identify and describe which technologies can be classified as ‘Fan-Out Packaging’ • To define clearly the different market classes of Fan-Out Packaging • To analyze key market drivers, benefits and challenges of Fan-Out packages by application • To describe the different existing technologies, their trends and roadmaps • To analyze the supply chain and Fan-Out landscape • To update the business status of Fan-Out technology markets • To provide a market forecast for the coming years, and estimate future trends Fan-Out Packaging markets are studied from the following angles: • Top-down based on end-systems demand • Market valuations based on top-down and bottom-up models • Market shares based on production projections • Supply value chain analysis • State-of-the-art technologies and trends • End-user application adoptions Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 SCOPE OFTHE REPORT Yours needs are out of scope of this report? Contact us for a custom study:
  5. 5. 5 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 REPORT METHODOLOGY & DEFINITIONS Market Volume (in Munits) ASP (in $) Revenue (in $M) Yole’s market forecast model is based on the matching of several sources: Information Aggregation Preexisting information
  6. 6. 6 Stefan Chitoraga Stefan Chitoraga is a Technology and Market Analyst specializing in Packaging and Assembly atYole Développement (Yole).As part of the Semiconductor, Memory & Computing division atYole, Stefan is focused on advanced packaging platforms and processes, substrates, and PCBs. He is involved daily in the production of technology & market reports and custom consulting projects. Stefan holds a Bachelor’s in Electronics and Computer Science for Industry Applications from the Polytech Grenoble (France). stefan.chitoraga@yole.fr Favier Shoo Favier Shoo is a Team Lead Analyst in the Packaging team within Semiconductor, Memory and Computing Division at Yole Développement (Yole), part ofYole Group of Companies. Based in Singapore, Favier manages an international team and develops the technical expertise and market know-how within the team. Favier also focuses on the production of technology & market reports, conducts strategic consulting and custom studies. Favier holds a Bachelor’s in Materials Engineering (Hons) and a Minor in Entrepreneurship from Nanyang Technological University (NTU) (Singapore). Favier was also the co-founder of a startup company where he formulated business goals, revenue models and marketing plans. favier.shoo@yole.fr Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 ABOUT THE AUTHORS Biographies & contacts
  7. 7. 7 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 GLOSSARY Abbreviation Meaning Abbreviation Meaning Abbreviation Meaning ADAS Advanced Driver-Assistance Systems HD FO High Density Fan-Out PMIC Power Management Integrated Circuit AiP Antenna in Package HDI High Density Interconnect PMU Power Management Unit APE Application Processor Engine HPC High Performance Computing PoP Package-on-Package APU Application Processor Unit HVM High-Volume Manufacturing PTOR Production Tool of Record ASIC Application-Specific Integrated Circuit I/O Inputs/Outputs PVD Physical Vapor Deposition BEOL Back-end Of Line IC Integrated Circuits PWB Printed Wiring Board BGA Ball Grid Array IDM Integrated Device Manufacturers QFN Quad-Flat No-Lead Package BOM Bill Of Materials inFO integrated Fan-Out Radar RAdio Detection And Ranging CAGR Compound Annual Growth Rate IP Intellectual Property RCC Resin Coated Copper CSP Chip Scale Package IPD Integrated Passive Devices RCP Redistributed Chip Package DSP Digital Signal Processor L/S Line/Space RDL Redistribution Layer DTOR Development Tool of Record LiDAR Light Detection and Ranging RF Radio Frequency ECD Electro-Chemical Deposition LTE Long-Term Evolution SiP System-in-Package EMC Epoxy Mold Compound LVM Low Volume Manufacturing SoC System-on-Chip ePLP embedded Package-Level-Packaging MCM Multi-Chip Module SoW System-on-Wafer ePoP embedded Package-on-Package MCP Multi-Chip Package TMV Through-Mold-Via eWLB embedded Wafer-Level BGA MEMS Micro-Electro-Mechanical System TPV Through-Package-Via F2F Face-to-Face mmWave Millimeter wave TSV Through-Silicon-Via FC Flip-Chip NR New Radio TTV Total Thickness Variation FO Fan-Out OEM Original Equipment Manufacturer UBM Under Bump Metallization FOPLP Fan-Out Panel-Level Packaging OSAT Outsource Semiconductor Assembly and Test UHD FO Ultra-High-Density Fan-Out FOWLP Fan-Out Wafer-level Packaging PA Power Amplifier WLCSP Wafer-Level Chip-Scale Package FPGA Field-Programmable Gate Array PCB Printed Circuit Board WLFO Wafer-Level Fan-Out HBM High Bandwidth Memory PDN Power Distribution Network
  8. 8. 8 3D-Plus, 3M,AGC,Amkor,Ajinomoto,AKG,Analog Devices,Apple,ASE,A*Star (IME), AT&S,Atotech,Aurora semiconductors, BASF, BK Ultrasound, Blackberry, Boschmann, Brewer Science, Broadcom, Bosch, Cerebras, China Mobile, Cirrus Logic, Cypress, DecaTechnologies, Denso, Dialog Semiconductor, Dow Dupont, Evatec, Fitbit, Freescale (NXP), Fujifilm, Global Foundry, Global Unichip Corp. (GUC), Google, Hella, HiSilicon, Hitachi chemicals, Huawei, Huatian, Infineon, Intel, Lenovo, LG Electronics, Marvell, Maxim IC, Mediatek, Medtronic, Nagase ChemteX, Nanium (Amkor), Nepes, Nepes Laweh, Nephos, Nokia, NXP, Oppo, Onda, PowertechTechnology Inc, Qualcomm, Qorvo, Rena, Rohm, Samsung, Schmoll maschinen, SEMCO, SEMSYSCO, Shinko Electric, Sivers IMA, Spectrum, SPIL, STATS ChipPAC (JCET), STMicroelectronics, Synaptics, Synergy,Texas Instruments,TSMC, Unimicron, Xilinx, Xiaomi and more… Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 COMPANIES CITED IN THIS REPORT
  9. 9. 9 Fan-Out Packaging can be understood in several ways depending on who we are talking to. It is especially confusing because when the hype around this package type began, many players used the name ‘Fan-Out’ to describe their solution to gain more attention in the market. An even more confusing aspect is that acknowledged Fan-Out solutions are not, or were not, called ‘Fan-Out’ by their creators. For instance, Infineon, creator of eWLB, one of the most widespread Fan-Out solutions, had not even called it ‘Fan-Out’ in its IP and referred to it for a long time as an ‘embedded die’ solution. An acknowledged characteristic of ‘Fan-Out’ packages is that, as the name suggests, interconnections are fanned out on the chip and because of that, bumping is not dependent on die surface. This means that Fan-Out has the potential to achieve any number of interconnects with standard pitches at any shrink stage of the wafer node technology. If the only definition of ‘Fan-Out’ is a package from which connections and bumping are out of the chip scale, then almost all packages can be defined as Fan- Out. Flip-Chip BGA, Flip-Chip CSP, Embedded Die, etc. Due to this, confusion is high in the industry. To make a fair comparison and to clarify the situation,Yole focuses on selected Fan-Out technologies that have at least one of these 2 key characteristics: Fan-Out solutions that use mold compound to embed the dies—not laminated materials. Fan-Out solutions that do not use IC substrates (PCB type of interposers) to fan out of chip area Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 DEFINITION OF FAN-OUT PACKAGING How different people can understand it, andYole’s focus Mold Chip No IC substrate (PCB type) used for fanning- out chip area Mold compound is used to embed the chip Connections are fanned out of chip scale area
  10. 10. 10 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT PACKAGING DEFINITION BY MARKET CLASS Core FO vs HD FO vs UHD FO RDL L/S Scaling (µm/µm) 5/5 10/10 ≥20/20 15/15 ≤2/2 I/O per mm2 >> 18 RDL L/S << 5/5µm 6 < I/O per mm2 < 12 15/15µm > RDL L/S > 5/5µm I/O per mm2 < 6 RDL L/S >15/15µm Core FO: Core Fan-Out HD FO: High-Density Fan-Out UHD FO: Ultra-High-Density Fan-Out Core FO1-2x RDL HD FO2-4x RDL UHD FO Fan-Out on Substrate IC Substrate I/O per Package Area ( I/O per mm 2 ) 4 >>18 12 6 ≤ 1 Core FO RF, PMU, BB,AiP etc. HD FO Mobile APE,AiP etc. UHD FO Networking, servers etc. In 2020 report, HD FO and UHD FO will be classified separately in order to be forward looking for market forecast due to the emergence of UHD FO
  11. 11. 11 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT PACKAGING REVENUE FORECASTS
  12. 12. 12 UHD FO 52% HD FO 37% Core FO 11% $3,425M Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT PACKAGING: REVENUE FORECAST 2020 2026 Total Fan-Out MarketValue CAGR2020-2026 =15.1% UHD FO 39% HD FO 37% Core FO 24% $1,475M
  13. 13. 13 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT PACKAGING REVENUE FORECASTS
  14. 14. 14 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT PACKAGING UNIT FORECASTS
  15. 15. 15 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT ACTIVITIES: GLOBAL MAP OF MAIN PLAYERS* *Showing mainly HQ. Non-exhaustive list of players: Included companies who have qualified or showed interest in Fan-Out… Former Nanium (Portugal) HQ Newly added companies/sites in 2021’s report The Philippines Korea JCAP China Korea Former Stats ChipPAC Singapore
  16. 16. 16 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT ACTIVITIES: GLOBAL MAP OF MANUFACTURERS Former Nanium (Portugal) The Philippines Korea JCAP China Korea Former Stats ChipPAC Singapore Amkor U.S. and Deca U.S. are no longer listed since these companies are not manufacturing in US. Non-exhaustive list of companies RCP Technology Other Fan-Out technology manufacturers eWLB Technology M-series Technology InFO Technology
  17. 17. 17 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT PACKAGING LATEST DEVELOPMENTS IN SUPPLY CHAIN Key summary of leaders within each business model EXISTING CUSTOMERS NEW CUSTOMERS SPECULATIVE CUSTOMERS FO SUPPLIER Leading Foundry: New customers since 2019… Leading IDM: More HD FO adoptions? Leading OSAT: New strategies and customers… Leading Licenser: New business model in 2020… ? Non-exhaustive list of companies
  18. 18. 18 Fan-Out’s role in this? Reducing single unit die size by integrating a number of smaller dies helps to improve the gross die yield. The industry players recognize this, and they are starting to split large dies into two or four smaller dies for processing, in order to resolve the yield loss and maintain the same bandwidth requirement by means of advanced packaging. There are few approaches that have potential to support higher die-to-die bandwidth. It can be either data rate boost from driver circuit enhancement or by increasing inter-chip RDL line density. For the former choice, the high data rate can be achieved at the cost of complex driver circuit, large die area, longer latency, or higher power consumption. Alternatively, fine line inter-chip interconnect can be deployed. Fan-Out Packaging is one of the technology that can potentially increase finer line interconnections between dies, without any FEOL processes, yet offer significant cost benefits with less production line/flow change and need for re-planning. As interconnections between multi-dies cater for more than 10 thousand I/Os, extremely fine pitch BGA substrate technology is necessary. However, it becomes a great challenge to BGA substrate manufacturing and causes loss on yield and increased cost. Moreover, the resulting reliability issues increase during the extreme environment test under high/low temperature and humidity conditions. Hence, many fabless players, like Mediatek and HiSilicon, have been actively qualifying UHD FO. Preliminary data (from MediaTek’s technical paper*) showed Fan-Out Packaging can handle the bandwidth and high speed SERDES signal. So, Fan-Out Packaging can indeed increase the gross die size and improve the wafer yield when the silicon die size is usually enormous and suffers low yield issues, especially in advanced wafer process. TSMC’s inFO_MiM (MUST-in-MUST) is targeting 3DIC stacking for HPC applications, to realize in-package near- memory computing. Lastly, Fan-Out Packaging’s relative cost, as compared to 2.5D Silicon interposers, is considered a cheaper alternative. Eventually, Fan-Out Packaging can find space in lower end side of higher-end applications. While Fan-Out Packaging role in HPCs is at its infancy stage, its potential is huge. Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 WHY IS FAN-OUT PACKAGING TRENDING IN HPC? *Source: Mediatek, “A Novel System in Package with Fan-out WLP for high speed SERDES application”, 2016 IEEE 66th Electronic Components and Technology Conference
  19. 19. 19 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT KEY APPLICATIONS Smartphones APE TSMC Apple APE series in Apple iPhone 7, Apple iPhone 8 and X, Apple iPhone XS and XR, Apple iPhone 11, 12 PMIC ASE, JCET, Amkor Marvell, Spreadtrum, Qualcomm Marvell PM820EAD in Onda Aurora 4G | Qualcomm PM 8150 in Samsung Galaxy S10| SPRD SC2712A in Lenovo A390t | Qualcomm PM 8150 Audio Codec ASE, JCET, Amkor Qualcomm Qualcomm WCD9326 in Redmi Note 3 | Qualcomm WCD9335 found in Samsung Galaxy S7 Edge | Headphone RF Transceivers ASE, JCET,Amkor Intel, Qualcomm, Qorvo Intel SMARTI UE2 in Samsung Galaxy S II I9100 | Qualcomm WTR2965 | Qorvo QPC1022 in LG Electronics V30 Baseband OSAT / IDM Intel INTEL XGOLD 116 in LG Electronics LG325G and Samsung C3312_DUOS RF Chip + AiP TSMC Apple iPhone 5G mmWave (AiP) [POTENTIAL] Smartwatches APE + PMIC Samsung Samsung Samsung Exynos 9110 in Samsung Galaxy Watch APE + Si Die TSMC Apple APE in Apple Watch Series 4 MCU + BT JCET Group Infineon (Cypress) CY 8 C 68237 FM BLE in Fitbit Charge 3 Headphones Audio Codec + PMIC OSAT Synaptic | Samsung SYNAPTICS SD0002 ARM-based USB-C audio interface found in AKG Headphones (SamsungGalaxy Note10+ & S20 Ultra 5G etc.) HPCs ASIC | FPGA + HBM TSMC, JCET & ASE MediaTek, GUC, Xilinx SerDes-based interface, Xilinx’s Artix®, Zynq® and Versal Series Cerebras WSE [POTENTIAL] Radar MMIC Infineon Denso and Continental DNMWR009 | NXP MR2001 in Continental ARS400 Radar | Infineon RASIC™ in Bosch MRR1Plus MMIC + AiP JCET Group Mediatek & Steelmate Mediatek’s Autus R10 MT2706 in Steelmate BSE151 Handheld Portable Ultrasound Amkor Portugal BK Medical BK Ultrasound Sonic Window Mobile & Consumer Telecom & Infrastructure Automotive & Mobility Medical END-MARKET Applications Devices Packaging Supplier *Fabless/IDM/OEM *Product/Model Name *Non-exhaustive list of companies and products Prototypes APE + NOR + PMIC Nepes, Infineon NXP, Cypress NXP SCM-iMX6Q HPCs ASIC TSMC Broadcom/Tesla Tesla 4.0 HW Full-Self-Driving Chip [POTENTIAL] Fan-Out Packaging
  20. 20. 20 UHD FO:TSMC INFO_OS & INFO_MS FOR HPCS TSMC’s UHD FO is addressing lower-cost HPCs TSMC led UHD FO with its inFO derivatives such as inFO_oS and inFO_MS for networking and AI inferencing applications respectively, in a mid-to-high end HPC market. Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 UHD FO packaging platforms like TSMC’s InFO_MS & inFO_oS offer an alternative solution to TSMC’s CoWoS for applications that seek cost/performance optimization in the mid-to-high end HPC market. TSMC is positioning CoWoS (2.5D interposer technology) as a premium high-density interconnected platform to offer high computing performance and high memory bandwidth to meet HPC AI training needs in clouds, data centers, and high-end servers. On the other hand, the InFO derivative technologies, InFO_oS, and inFO_MS, offer the best cost/performance integration solution for specific HPC applications, such as networking and low-latency AI inference, respectively. Source: TSMC Significant cost reduction is achieved by splitting a large advanced node networking chip, such as network processor and network switch, into several small networking chips on InFO_oS package through high density, high speed interconnects. Cost-performance improvements through chiplet Integration inFO_oS for re-integrating smaller network chiplets InFO_MS integrates advanced SoC and HBM for AI Inferencing inFO inFO InFO_MS integrates advanced node GPU,ASIC, with HBMs to support HPC applications such as fine pitch SERDES interconnects featuring high data rate and high memory data bandwidth communication between compute die and HBM memory. Source: TSMC Source: TSMC
  21. 21. 21 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 VOLUME PRODUCTION ROADMAP FOR FOWLP Key parameters Roadmap described here is for volume production and an expected average of the different technologies on the market. Parameters ≤ 2018 2019 2020 2021 2022 2023 2024 2025 2026 Maximum package size Side-by-Side Die Max level of RDL Min. Line/Space Package minimum thickness (without BGA) Minimum die size (X–Y directions) Maximum die size (X–Y directions) Minimum bump pitch Minimum die-to- die distance 15x15mm >>25x25mm 3x RDL 4x RDL 8/8µm 5/5µm 2/2µm 250µm 200µm 150µm 900µm 500µm 200µm 10mm 12mm 15mm 400µm 350µm 250µm 200µm 150µm 2~3 2~4
  22. 22. 22 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT PACKAGING TECHNOLOGY ROADMAP: DIFFERENT END-MARKET Exists in “Automotive & Transportation” and “Medical” Core Fan-Out New potential in “Automotive & Transport” - Sensors Not found in any other market apart from “Mobile & Consumer” HD Fan-Out New potential in “Telecom & Infrastructure” - 5G PAST to PRESENT FUTURE* 0 100 300 500 1000 1500 I/O counts Mixed Signal ASIC, RF >2000 « Ultra-High-Density Fan-Out » Area of Interest « Core Fan-Out » Area of Interest UHD FO: Ultra-High-Density Fan-Out High performance capability with FO on Substrate. Core FO → HD FO: Driver of higher integration in MEMS applications by SiP Low-End Mid-End High-Performance High-End UHD Fan-Out Qualification: “Telecom & Infrastructure” - Data Centers and AI « High Density Fan-Out » Area of Interest Development Time *Future potential applications gathered from technical paper interest and interviews ≤2016 2017 2021 2022 2023 2024 2025 2026 2019 2020 2018
  23. 23. 23 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 FAN-OUT PACKAGING TECHNOLOGIES TSMC: New InFO technologies and summary Metrics inFO_PoP inFO_oS & inFO_MS inFO_SoW inFO_AiP inFO_MiM PRODUCTION HVM since 2016 LVM since 2019 Qualification LVM expected by end of 2021 Qualification LVM expected in 2023 Qualification STATUS High-volume production of Gen-3 Successful qualification of Gen-4 Successful qualification of 7nm multi-die integration. Enable 97% reduction in PDN (Power Distribution Network) impedance Enable low transmission loss and high antenna performance for mmWave system Validated better performance as compared to FC. APPLICATION Mobile APE+Memory: Smartphone, smartwatches, tablets High Performance Computing: Al chips, servers; networking High Performance Computing HW 4.0 self-driving chip mmWave wireless communication: 5G, Wi-Fi, Modems, sensors Advanced Mobile & HPC. BENEFITS Integrate systems with lower TTV as compared to FC, at finer L/S for board- level I/O Enable better yield as compared to a single large die SoC 15% power saving of the interconnects with length of 30 mm Enable low transmission loss and high antenna performance for mmWave system Validated and simulated better performance and form factor as compared to FC and TSV. SCHEMATIC Source: TSMC [Online]. Available: https://www.tsmc.com/english/dedicatedF oundry/technology/InFO.htm [Accessed: 16-Apr-2021] Source: “inFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System Integration” TSMC: ECTC, 2018 Source: TSMC [Online]. Available: https://www.tsmc.com/english/dedicatedF oundry/technology/InFO.htm [Accessed: 16-Apr-2021] Source: “3D-MiM (MUST-in-MUST) Technology for Advanced System Integration” TSMC: ECTC, 2019 inFO leads APE Packaging in mobile and continues to develop and penetrate new high-end applications Source: “InFO_SoW (System-on-Wafer) for High Performance Computing” TSMC: ECTC, 2020
  24. 24. 24 READINESS FOR FOPLP PTI, Nepes Laweh & Samsung Electronics have entered production in 2018.We are expecting these players to continue production through 2020. ASE is expected to be running HVM by 2022. ESWIN is potentially the first FOPLP player in China to run LVM production by 2022 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 Manufacturers ≤ 2017 2018 2019 2020 2021 2022 2023 2024 R&D Sampling+LVM HVM
  25. 25. 25 FAN-OUT PRODUCTION CARRIERS: FOWLPVS FOPLP PENETRATION RATE Panel will progressively take a share of production but still in a limited way. FOPLP is expected to take off when big die applications are adopted. Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 Fan-Out Packaging Production, 300mm wfr eq. (%) By Carrier Types 200mm (300mm Wfr Eq) 300mm Panel (300mm Wfr Eq)
  26. 26. 26 Contact our SalesTeam for more information Advanced Packaging Quarterly Market Monitor Status of the Advanced Packaging Industry 2020 5G PackagingTrends for Smartphones 2021 Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 YOLE GROUP OF COMPANIES RELATED REPORTS Yole Développement
  27. 27. 27 Contact our SalesTeam for more information Fan-Out Packaging Processes Comparison 2020 HiSilicon Hi1382 Coherent Processor with ASE’s FOCoS Fan-Out WLP and PLP Technologies 2021 | Sample | www.yole.fr | ©2021 YOLE GROUP OF COMPANIES RELATED REPORTS System Plus Consulting
  28. 28. 28 Yole Group of Companies, including Yole Développement, System Plus Consulting and PISEO, are pleased to provide you a glimpse of our accumulated knowledge. We invite you to share our data with your own network, within your presentations, press releases, dedicated articles and more, but you first need approval from Yole Public Relations department. If you are interested, feel free to contact us right now! We will also be more than happy to give you updated data and appropriate formats. Your contact: Sandrine Leroy, Dir. Public Relations Email: leroy@yole.fr HOWTO USE OUR DATA? About Yole Développement | www.yole.fr | ©2021
  29. 29. © 2021 From Technologies to Markets Yole Développement Who are we?
  30. 30. 30 ©2019 | www.yole.fr | About Yole Développement FIELDS OF EXPERTISE COVERING THE SEMICONDUCTOR INDUSTRY Semiconductor, Memory & Computing o Semiconductor Packaging and Substrates o Semiconductor Manufacturing o Memory o Computing and Software Power & Wireless o RF Devices & Technologies o Compound Semiconductors & Emerging Materials o Power Electronics o Batteries & Energy Management Photonics & Sensing o Photonics o Lighting o Imaging o Sensing & Actuating o Display About Yole Développement | www.yole.fr | ©2021
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  35. 35. 35 A UNIQUE AND PROVEN METHODOLOGY › Market segmentation › Per application › Per technical needs › Per technology adoption and behavior of the supply chain MARKET › Top to bottom › Industry organizations › Aggregate of market forecasts at system and device levels up to the wafer and equipment › Bottom-up › Ecosystem analysis › Aggregate of all players’ revenue at device, module and system levels › In unit, dollar and wafer BOTTOM-UP &TOP-TO-BOTTOM › Technology analysis › Competitive landscape › Technology comparison › Reverse costing › Reverse engineering › Technology life cycle › Development cycles › Adoption by the supply chain › HV manufacturing and evolutions TECHNOLOGY Thanks to its marketing approach, its understanding of the industrial and technical environment and information collection, Yole Développement can assist companies at every stage of their growth. About Yole Développement | www.yole.fr | ©2021
  36. 36. 36 OUR NETWORK IS THE ENTIRE SUPPLY CHAIN ACROSS 6 MARKETS Integrators, end-users and software developers Device manufacturers Suppliers: material, equipment, OSAT, foundries… Financial investors, R&D centers Mobile & Consumer Automotive & Mobility Telecom & Infrastructure Medical Industrial Defense & Aerospace 6 key markets About Yole Développement | www.yole.fr | ©2021
  37. 37. 37 About Yole Développement | www.yole.fr | ©2020 CONTACTS Western US & Canada Steve Laferriere - steve.laferriere@yole.fr + 1 310 600 8267 Eastern US & Canada ChrisYouman - chris.youman@yole.fr +1 919 607 9839 Europe and RoW Lizzie Levenez - lizzie.levenez@yole.fr +49 15 123 544 182 Benelux, UK & Spain Marine Wybranietz - marine.wybranietz@yole.fr +49 69 96 21 76 78 India and RoA Takashi Onozawa - takashi.onozawa@yole.fr +81 80 4371 4887 Greater China MavisWang - mavis.wang@yole.fr +886 979 336 809 +86 136 6156 6824 Korea Peter Ok - peter.ok@yole.fr +82 10 4089 0233 Japan Miho Ohtake - miho.ohtake@yole.fr +81 34 4059 204 Japan and Singapore Itsuyo Oshiba - itsuyo.oshiba@yole.fr +81 80 3577 3042 Japan Toru Hosaka – toru.hosaka@yole.fr +81 90 1775 3866 FINANCIAL SERVICES › Jean-Christophe Eloy - eloy@yole.fr +33 4 72 83 01 80 › Ivan Donaldson - ivan.donaldson@yole.fr +1 208 850 3914 CUSTOM PROJECT SERVICES › Jérome Azémar, Yole Développement - jerome.azemar@yole.fr - +33 6 27 68 69 33 › Julie Coulon, System Plus Consulting - jcoulon@systemplus.fr - +33 2 72 17 89 85 GENERAL › Sandrine Leroy, Public Relations sandrine.leroy@yole.fr - +33 4 72 83 01 89 › General inquiries: info@yole.fr - +33 4 72 83 01 80 Follow us on REPORTS, MONITORS &TRACKS About Yole Développement | www.yole.fr | ©2021
  • JoyceChen3

    Jul. 28, 2021

TSMC’s Fan-Out success with Apple and high-performance computing are pushing Intel, Samsung, ASE, and all other competitors to find new innovative solutions. More information: https://www.i-micronews.com/products/fan-out-wlp-and-plp-applications-and-technologies-2021/

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