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CACHE MEMORY


                               Maninder Kaur
                             professormaninder@gmail.com




1   www.eazynotes.com                        24-Nov-2010
What is Cache Memory?
    ï‚—Cache memory is a small, high-speed RAM buffer located
      between the CPU and main memory.

    ï‚—Cache memory holds a copy of the instructions (instruction
      cache) or data (operand or data cache) currently being used
      by the CPU.

    ï‚—The main purpose of a cache is to accelerate your computer
      while keeping the price of the computer low.


2   www.eazynotes.com                                     24-Nov-2010
Placement of Cache in computer




3   www.eazynotes.com         24-Nov-2010
Hit Ratio
    ï‚—The ratio of the total number of hits divided by the total
      CPU accesses to memory (i.e. hits plus misses) is called Hit
      Ratio.

    ï‚—Hit Ratio = Total Number of Hits / (Total
                        Number of Hits + Total Number of
                                                      Miss)




4   www.eazynotes.com                                      24-Nov-2010
Example
    A system with 512 x 12 cache and 32 K x 12 of
    main memory.




5     www.eazynotes.com                      24-Nov-2010
Types of Cache Mapping

        1.     Direct Mapping

        2.     Associative Mapping

        3.     Set Associative Mapping


6   www.eazynotes.com                    24-Nov-2010
1. Direct Mapping
    ï‚— The direct mapping technique is simple and inexpensive to implement.

    ï‚— When the CPU wants to access data from memory, it places a address. The
       index field of CPU address is used to access address.
    ï‚— The tag field of CPU address is compared with the associated tag in the word
       read from the cache.
    ï‚— If the tag-bits of CPU address is matched with the tag-bits of cache, then there
       is a hit and the required data word is read from cache.
    ï‚— If there is no match, then there is a miss and the required data word is stored in
       main memory. It is then transferred from main memory to cache memory with
       the new tag.




7   www.eazynotes.com                                                        24-Nov-2010
1. Direct Mapping




8   www.eazynotes.com                  24-Nov-2010
1. Direct Mapping




9   www.eazynotes.com                  24-Nov-2010
2. Associative Mapping
     ï‚—An associative mapping uses an associative memory.

     ï‚—This memory is being accessed using its contents.

     ï‚—Each line of cache memory will accommodate the address
       (main memory) and the contents of that address from the
       main memory.
     ï‚—That is why this memory is also called Content Addressable
       Memory (CAM). It allows each block of main memory to be
       stored in the cache.



10   www.eazynotes.com                                     24-Nov-2010
2. Associative Mapping




11   www.eazynotes.com             24-Nov-2010
3. Set Associative Mapping
     ï‚—That is the easy control of the direct mapping cache and the
       more flexible mapping of the fully associative cache.
     ï‚— In set associative mapping, each cache location can have
       more than one pair of tag + data items.
     ï‚—That is more than one pair of tag and data are residing at the
       same location of cache memory. If one cache location is
       holding two pair of tag + data items, that is called 2-way set
       associative mapping.



12   www.eazynotes.com                                         24-Nov-2010
3. Two-Way Set Associative
                    Mapping




13   www.eazynotes.com              24-Nov-2010
Replacement Algorithms of
                  Cache Memory
     ï‚— Replacement algorithms are used when there are no available space in a cache in which
       to place a data. Four of the most common cache replacement algorithms are described
       below:
     ï‚— Least Recently Used (LRU):
        ï‚— The LRU algorithm selects for replacement the item that has been least recently used by
           the CPU.

     ï‚— First-In-First-Out (FIFO):
        ï‚— The FIFO algorithm selects for replacement the item that has been in the cache from the
           longest time.

     ï‚— Least Frequently Used (LRU):
        ï‚— The LRU algorithm selects for replacement the item that has been least frequently used
           by the CPU.

     ï‚— Random:
        ï‚— The random algorithm selects for replacement the item randomly.



14   www.eazynotes.com                                                               24-Nov-2010
Writing into Cache
     ï‚—When memory write operations are performed, CPU first
       writes into the cache memory. These modifications made by
       CPU during a write operations, on the data saved in cache,
       need to be written back to main memory or to auxiliary
       memory.

     ï‚—These two popular cache write policies (schemes) are:
        ï‚—Write-Through
        ï‚—Write-Back




15   www.eazynotes.com                                   24-Nov-2010
Write-Through
     ï‚—In a write through cache, the main memory is updated each
       time the CPU writes into cache.

     ï‚—The advantage of the write-through cache is that the main
       memory always contains the same data as the cache contains.

     ï‚—This characteristic is desirable in a system which uses direct
       memory access scheme of data transfer. The I/O devices
       communicating through DMA receive the most recent data.



16   www.eazynotes.com                                       24-Nov-2010
Write-Back
     ï‚—In a write back scheme, only the cache memory is updated
       during a write operation.

     ï‚—The updated locations in the cache memory are marked by a
       flag so that later on, when the word is removed from the
       cache, it is copied into the main memory.

     ï‚—The words are removed from the cache time to time to make
       room for a new block of words.


17   www.eazynotes.com                                    24-Nov-2010
18   Jan 26, 2013   www.eazynotes.com

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Cache memory

  • 1. CACHE MEMORY Maninder Kaur professormaninder@gmail.com 1 www.eazynotes.com 24-Nov-2010
  • 2. What is Cache Memory? ï‚—Cache memory is a small, high-speed RAM buffer located between the CPU and main memory. ï‚—Cache memory holds a copy of the instructions (instruction cache) or data (operand or data cache) currently being used by the CPU. ï‚—The main purpose of a cache is to accelerate your computer while keeping the price of the computer low. 2 www.eazynotes.com 24-Nov-2010
  • 3. Placement of Cache in computer 3 www.eazynotes.com 24-Nov-2010
  • 4. Hit Ratio ï‚—The ratio of the total number of hits divided by the total CPU accesses to memory (i.e. hits plus misses) is called Hit Ratio. ï‚—Hit Ratio = Total Number of Hits / (Total Number of Hits + Total Number of Miss) 4 www.eazynotes.com 24-Nov-2010
  • 5. Example A system with 512 x 12 cache and 32 K x 12 of main memory. 5 www.eazynotes.com 24-Nov-2010
  • 6. Types of Cache Mapping 1. Direct Mapping 2. Associative Mapping 3. Set Associative Mapping 6 www.eazynotes.com 24-Nov-2010
  • 7. 1. Direct Mapping ï‚— The direct mapping technique is simple and inexpensive to implement. ï‚— When the CPU wants to access data from memory, it places a address. The index field of CPU address is used to access address. ï‚— The tag field of CPU address is compared with the associated tag in the word read from the cache. ï‚— If the tag-bits of CPU address is matched with the tag-bits of cache, then there is a hit and the required data word is read from cache. ï‚— If there is no match, then there is a miss and the required data word is stored in main memory. It is then transferred from main memory to cache memory with the new tag. 7 www.eazynotes.com 24-Nov-2010
  • 8. 1. Direct Mapping 8 www.eazynotes.com 24-Nov-2010
  • 9. 1. Direct Mapping 9 www.eazynotes.com 24-Nov-2010
  • 10. 2. Associative Mapping ï‚—An associative mapping uses an associative memory. ï‚—This memory is being accessed using its contents. ï‚—Each line of cache memory will accommodate the address (main memory) and the contents of that address from the main memory. ï‚—That is why this memory is also called Content Addressable Memory (CAM). It allows each block of main memory to be stored in the cache. 10 www.eazynotes.com 24-Nov-2010
  • 11. 2. Associative Mapping 11 www.eazynotes.com 24-Nov-2010
  • 12. 3. Set Associative Mapping ï‚—That is the easy control of the direct mapping cache and the more flexible mapping of the fully associative cache. ï‚— In set associative mapping, each cache location can have more than one pair of tag + data items. ï‚—That is more than one pair of tag and data are residing at the same location of cache memory. If one cache location is holding two pair of tag + data items, that is called 2-way set associative mapping. 12 www.eazynotes.com 24-Nov-2010
  • 13. 3. Two-Way Set Associative Mapping 13 www.eazynotes.com 24-Nov-2010
  • 14. Replacement Algorithms of Cache Memory ï‚— Replacement algorithms are used when there are no available space in a cache in which to place a data. Four of the most common cache replacement algorithms are described below: ï‚— Least Recently Used (LRU): ï‚— The LRU algorithm selects for replacement the item that has been least recently used by the CPU. ï‚— First-In-First-Out (FIFO): ï‚— The FIFO algorithm selects for replacement the item that has been in the cache from the longest time. ï‚— Least Frequently Used (LRU): ï‚— The LRU algorithm selects for replacement the item that has been least frequently used by the CPU. ï‚— Random: ï‚— The random algorithm selects for replacement the item randomly. 14 www.eazynotes.com 24-Nov-2010
  • 15. Writing into Cache ï‚—When memory write operations are performed, CPU first writes into the cache memory. These modifications made by CPU during a write operations, on the data saved in cache, need to be written back to main memory or to auxiliary memory. ï‚—These two popular cache write policies (schemes) are: ï‚—Write-Through ï‚—Write-Back 15 www.eazynotes.com 24-Nov-2010
  • 16. Write-Through ï‚—In a write through cache, the main memory is updated each time the CPU writes into cache. ï‚—The advantage of the write-through cache is that the main memory always contains the same data as the cache contains. ï‚—This characteristic is desirable in a system which uses direct memory access scheme of data transfer. The I/O devices communicating through DMA receive the most recent data. 16 www.eazynotes.com 24-Nov-2010
  • 17. Write-Back ï‚—In a write back scheme, only the cache memory is updated during a write operation. ï‚—The updated locations in the cache memory are marked by a flag so that later on, when the word is removed from the cache, it is copied into the main memory. ï‚—The words are removed from the cache time to time to make room for a new block of words. 17 www.eazynotes.com 24-Nov-2010
  • 18. 18 Jan 26, 2013 www.eazynotes.com