Presentation by Vladimir Gurevich at the Dataplane Acceleration Developer Day 2016 in Nov 2016 - http://open-nfp.org/dxdd/

1. Copyright © 2016 - Barefoot Networks
Programmable Data Plane at Terabit Speeds
Vladimir Gurevich

2. Copyright © 2016 - Barefoot Networks
The Three Planes
• Independent software
components
◦ Implement different classes of
algorithms
◦ Have different design requirements
◦ Are designed using different
methodologies
◦ Are Implemented using different
languages
■ Or different hardware
◦ Run Independently
◦ Communicate through well-defined
interfaces
2
Management Plane
Configuration CLI/GUI/SNMP...
Control Plane
Protocol Stacks Port
Mgmt
Platform
Mgmt
OSPF
STP
IS-IS
PIM-SM
BGP
Data Plane
Packet Forwarding

3. Copyright © 2016 - Barefoot Networks
Switch OS
Run-time API
Driver
“This is how I know to
process packets”
(i.e. the ASIC datasheet
makes the rules)
Fixed-function ASIC
Bottoms-up network element design
Network Demands
3

4. Copyright © 2016 - Barefoot Networks
Switch OS
Run-time API
Driver
“This is how I want the
network to behave and how to
switch packets…”
(the user / controller
makes the rules)
Barefoot Tofino + P4
Top-down network element design
Network Demands
P4
Feedback
4

5. Copyright © 2016 - Barefoot Networks
Fixed Function Switches
Switch OS
Static Run-time API
Driver
Fixed Meta-Data
Traffic
Manager
Fixed
Parser
Fixed
Lookups
Fixed
Memories
Fixed
Actions
Fixed
Lookups
Fixed
Memories
Fixed
Actions
Fixed
Lookups
Fixed
Memories
Fixed
Actions
Fixed
Lookups
Fixed
Memories
Fixed
Actions
Fixed
Packet
Mods
Fixed Function ASIC
5

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Programmable Switch Approach
Fixed Meta-Data
Traffic
Manag
er
Fixed
Parser
Fixed
Looku
ps
Fixed
Memories
Fixed
Looku
ps
Fixed
Looku
ps
Fixed
Memories
Fixed
Looku
ps
Fixed
Looku
ps
Fixed
Memories
Fixed
Looku
ps
Fixed
Looku
ps
Fixed
Memories
Fixed
Looku
ps
Fixed
Packe
t
Mods
Programmable Meta-Data
Traffic
Manager
Programmable
Parser
Flexible
Lookups
Shared
Memories
Custom
Actions
Flexible
Lookups
Shared
Memories
Custom
Actions
Flexible
Lookups
Shared
Memories
Custom
Actions
Flexible
Lookups
Shared
Memories
Custom
Actions
DeParser
Programmable ASIC
switch.p4
Protocol
Authoring
1
Compile
2
Configure
3
Auto Generated
Run-time API
6

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Result: Customer Defined Switch
Switch OS
Driver
User Defined Meta-Data
Traffic
Manager
User
Defined
Parser
User
Defined
Lookups
User Defined
Tables
User
Defined
Actions
User
Defined
Lookups
User Defined
Tables
User
Defined
Actions
User
Defined
Lookups
User Defined
Tables
User
Defined
Actions
User
Defined
Lookups
User Defined
Tables
User
Defined
Actions
User
Defined
DeParser
Programmable ASIC : User Defined Forwarding Plane
Run!
4
Add/delete table rules
Auto Generated
Run-time API
7

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Match-Action Packet Processing Concept
8
Programmable
Parser
Match
Memory
Action
ALU

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Programmable
Parser
PISA: Protocol Independent Switch Architecture
Ingress EgressBuffer

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Programmable
Parser
PISA: Protocol Independent Switch Architecture
Mix of SRAM and TCAM for: lookup tables,
counters, meters, Bloom filters
ALUs for: Standard Boolean and Arithmetic
Operations & add/delete fields, hashes
Recirculation
Programmable
Packet Generator

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What Happens Inside?
Queues
Programmable
Parser
CLK
…
…
…
…
Match Table
(SRAM or TCAM)
Cross
Bar
PHV
(Packet Header Vector) PHV’
action
11

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P4 Visualizations (PHV Allocation)
12

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P4 Visualizations (Resource Allocation)
13

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P4 Visualizations (Resource Usage Summary)
14

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Tofino Block Diagram
Rx MACs
10/25/40/50/100
Ingress
Pipeline
Tx MAC
10/25/40/50/100
Control & Configuration
Reset /
Clocks
PCIe
CPU
MAC
DMA
engines
Rx MACs
10/25/40/50/100
Ingress
Pipeline
Tx MAC
10/25/40/50/100
Rx MACs
10/25/40/50/100
Ingress
Pipeline
Tx MAC
10/25/40/50/100
Rx MACs
10/25/40/50/100
Ingress
Pipeline
Tx MAC
10/25/40/50/100
Traffic
Manager
Egress
Pipeline
Egress
Pipeline
Egress
Pipeline
Egress
Pipeline

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Barefoot SDE
16
Tofino:
Best-in-class P4 Targets
Chip Driver
Protocol-independent API
Your Auto-generated API
Your P4
Program
Your Control-plane Program (Apps)
ASIC
Model
Barefoot
Compiler
& Dev. Tools
Add/delete table rules
at run time
Behavioral
Model

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Reference P4
Program + Your
Custom Features
Barefoot
Compiler
& Dev. Tools
Barefoot SDE
17
Tofino:
Best-in-class P4 Targets
Chip Driver
Protocol-independent API
Your Auto-generated API
Your Control-plane Program (Apps)
ASIC
Model
Behavioral
Model
SwitchAPI
OCP SAI (Switch Abstraction
Interface)
Open
source
PacketTestFramework

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switch.p4 & switchAPI Features
18
TCP New
IPv4 IPv6
VLANEth
Parser Ingress Match+Action Egress Match+ActionQueues
switch.p4
Switch OS
Run-time API
Auto-generate
Add/delete table rules
Driver
Protocol
Authoring
1
Compile
2
Configure
3
Run!
4
IPv4 and IPv6 routing
- Unicast
- Unicast RPF
- Strict and Loose
- Multicast
- PIM-SM/DM & PIM-BiDir
L2 switching
- Learning
- STP state
- VLAN Translation
Load balancing
- WECMP, ECMP and LAG
- Resilient Hashing
Tunneling
- IPv4 & IPv6 Routing & Switching
- IP-in-IP (6in4, 4in4)
- VXLAN, NVGRE, GENEVE & GRE
MPLS
- LER
- LSR
- IPv4/v6 routing (L3VPN)
- L2 switching (EoMPLS, VPLS)
ACL
- MAC ACL,
- IPv4/v6 ACL/RACL,
- QoS ACL
- System ACL
- PBR (Policy based routing)
NAT
QOS
- QoS Classification & marking
- Drop profiles/WRED
- RoCE v2 & FCoE
- CoPP (Control plane policing)
Security Features
- Storm Control, IP Source Guard
Mirroring
- Ingress Mirroring and Egress Mirroring
- Negative Mirroring
Counters
- Route Table Entry Counters
- VLAN/Bridge Domain Counters
- Port/Interface Counters
Protocol Offload
- BFD, OAM
Multi-chip Fabric Support
- Forwarding, QOS

19. Copyright © 2016 - Barefoot Networks
Thank you