VLSI

1. DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING
Question Bank (2016-17)
SUBJECT: VLSI DESIGN (IV/I) JNTUK-R13
UNIT-I
PART –A
1. Explain the depletion mode transistor action.
2. Define the following terms: (a) trans conductance ( b ) output conductance ( c ) figure of
merit (d) threshold voltage
3. What is latch up in CMOS transistors and how to overcome it?
4. Explain the various steps in PMOS fabrication.
PART –B
1. With neat diagrams, explain the different steps in n-well fabrication of CMOS transistors.
2. Discuss fabrication differences between NMOS and CMOS technologies. Which fabrication is
preferred and why?
3. Draw the Id vs vss. characteristics of a MOS transistor and explain its various regions of
operation.
4. Explain the working of a BiCMOS transistor
5. With neat sketches explain the formation of the inversion layer in P-channel Enhancement
MOSFET.
6. Derive the expression for drain current of a CMOS transistor
7. Draw the BiCMOS inverter circuit and explain its working
8. Determine the pull up to pull down ration for the inverter driven by transmission gates.
9. Draw the basic MOS transistor physical structure and explain its working.
UNIT-II
PART –A
1. What are the different steps in the stick layout using nMOS design?
2. Explain the double metal MOS process rules.
3. What are the different design rules for wires and contacts?
4. Draw the stick diagram for CMOS inverter.
PART –B
1. Draw the basic MOS transistor physical structure and explain its working.
2. Draw the circuit diagram, layout diagram and stick diagram for CMOS two input NAND gate
and explain its working.
3. What are the different steps in the stick layout using CMOS design?
4. Explain CMOS lambda based design rules
5. Write design rules for the following: (a) wires ( b ) contacts ( c ) transistor ( d ) diffusion
6. Design a stick diagram for two input CMOS NAND and NOR gates.
7. Design stick diagram for the function F = (A+B)(C+D)
8. Design CMOS layout for the function Y = (A.B+C+D)
9. Explain the color code used for drawing stick diagram for NMOS and PMOS designs.
10. What are the different types of contact cuts made during the fabrication of an IC? Which one is
commonly used and why?
UNIT-III
PART –A
1. Explain about scaling models and scaling factors.
2. Explain how MOSFETs can be used as switches
3. What is inverter delay? How delay is calculated for multiple stages?
4. what is switch logic ? write some examples.
PART –B
1. Describe three sources of writing capacitances. Explain the effect of writing capacitance on the
performance of a VLSI circuit
2. Explain different series and parallel combinations of push-up and pull-down networks
3. Derive the propagation delay τPHL for inverter.
4. Draw the circuit diagram of complementary pass logic implementation of NAND/AND gate and
explain its working.

2. 5. Explain different types of capacitor loads for MOS transistors.
6. The equivalent input capacitance Cin of an inverter is 0.01pF and the delay time when its load
is an identical size inverter is 1ns. This inverter is used to drive an output pin with a
capacitance of CL =11pF. For a minimum average delay time, how many buffering inverters
should be used? What is the minimum average delay time
7. Determine the average dynamic power dissipation in the inverter.
8. Determine the τ for an inverter with Ln=Lp = 2µm, Wn=Wp=4µm
9. Explain the methods to improve the fan in and fan out capacity of gates.
10. If two inverters are used to form a non inverting buffer between the circuit and the 150pF
capacitor, determine the dimensions of the transistors used in these two inverters so that the
delay time form the circuit input to the 150pF capacitor is minimized.
11. All the transistors used in a multiple level circuit have dimensions of W=6µm and L=6µm. This
circuit has a delay of 50ns when its load is a minimum size inverter (i.e., W=4µm and
L=2µm). Consider only channel resistance and gate capacitance in the following problems. If
the load is replaced by a 50pF capacitor, what is the delay time?
12. What are the different scaling factors? How these change the device parameters?
UNIT-IV
PART –A
1. Design a two input XOR gate using a ROM.
2. Explain Clocked sequential circuits.
3. What are General considerations of subsystem design processes
4. What are the limitations due to current density?
PART –B
1. Explain how the transistor might be sized to optimize the delay through the carry stage in
parallel adder.
2. Differentiate between PROM, PAL and PLA.
3. Implement a 3 bit synchronous counter using PAL.
4. Explain the Barrel Shifter operation with its circuit diagram.
5. Explain the operation of zero/one detector.
6. Draw the circuit diagram of six transistor SRAM cell and explain its working
7. Draw and explain the structure of an n-MOS ROM.
8. With neat circuit diagram, explain the operation of (a) Carry look ahead adder (b) Barrel
shifter.
9. Discuss some architectural issues in VLSI designing.
10. Switch logic, Gate logic, examples of structured design.
UNIT-V
PART –A
1. Explain global routing in VLSI design
2. Compare PAL, PLA and CPLD in various aspects.
3. What are the limitations due to sub threshold currents?
4. Describe the design strategies for CMOS testing.
5. What are the advantages of designing using standard cells?
6. b) How random test generation is used for verification?
PART –B
1. What is meant by CMOS testing? Explain the need for testing.
2. Explain the concept of layout design for improved testability with suitable example.
3. Describe the various design strategies used for CMOS testing.
4. Write notes on system-level CMOS testing techniques.
5. Discuss about layout design for improved testability. Consider a suitable example.
6. Explain the CMOS testing principles.
7. What are the system-level test techniques? Explain one of them with an example.
8. Compare full custom and semi custom standard cell VLSI designing?
9. What are the α and β factors? How these are used in VLSI designing?
10. What are the various PLDs? How these are used in VLSI designing?
11. What is standard cell? How this is used in VLSI designing.
12. What are the various gate level verification tools? Compare them.

3. 13. Design logic diagram using PLA for the function f = Σ m (0, 1, 3, 5, 7, 11, 14) + Σ ф (2, 6)
diagram.
14. Explain look up table (LUT) of FPGA with circuit diagram.
15. Implement a 3 bit synchronous counter using PAL.
16. How simulation is a very powerful technique in verifying a chip’s timing characteristics?
UNIT-VI
PART –A
1. What is configuration bonding? Write its syntax in VHDL.
2. What is net list? How it is used in VLSI design?
3. What are the different objects and classes in VHDL programming? Write some examples.
4. Explain how packages, libraries and subprograms are written in VHDL?
5. List the various VHDL verification tools and explain any one of them.
6. What is mean by hardware simulation and synthesis?
PART –B
1. What are the different data types available in VHDL and how they are indicated?
2. Write VHDL program for a 4-bit counter with asynchronous reset.
3. Explain how a FSM model is described in VHDL with suitable program.
4. What is the difference between design capture tools and design verification tools? Give some
examples of each.
5. Write short notes on following: (a) Technology Libraries. (b) Post layout timing simulation. (c)
Static timing.
6. With respect to synthesis process. Explain the following: [15] (a) Flattering (b) Factoring (c)
Mapping.
7. How to test the post layout and explain timing simulation for it?
8. Write a VHDL program for two bit full adder using NAND gates in structural model.
9. How to place the blocks in VLSI design and explain how to optimize it?
10. Write a VHDL program for decade counter.
11. Compare VHDL and Verilog HDL with suitable example.
12. Write a VHDL program for a 8x1 mux using 2x1 mux.