6. initial
#32 $finish;
initial begin
// Initialize Inputs
in = 0;
sh = 0;
shift_LeftRight = 0;
rotate_LeftRight = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
7. 8 BIT BOOTH MULTIPLIER
module multiplier(prod, busy, mc, mp, clk, start);
output [15:0] prod;
output busy;
input [7:0] mc, mp;
input clk, start;
reg [7:0] A, Q, M;
reg Q_1;
reg [7:0] count;
wire [7:0] sum, difference;
8. always @(posedge clk)
begin
if (start) begin
A <= 8'b0;
M <= mc;
Q <= mp;
Q_1 <= 1'b0;
count <= 7'b0;
end
else begin
case ({Q[0], Q_1})
2'b01 : {A, Q, Q_1} <= {sum[7], sum, Q};
2'b10 : {A, Q, Q_1} <= {difference[7], difference, Q};
default: {A, Q, Q_1} <= {A[7], A, Q};
endcase
count <= count + 1'b1;
end
end
alu adder (sum, A, M, 1'b0);
alu subtracter (difference, A, ~M, 1'b1);
assign prod = {A, Q};
assign busy = (count < 8);
endmodule
//The following is an alu.
9. //It is an adder, but capable of subtraction:
//Recall that subtraction means adding the two's complement-//a - b = a + (-b) = a + (inverted b + 1)
//The 1 will be coming in as cin (carry-in)
module alu(out, a, b, cin);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
TEST BENCH
module boothm_tb;
// Inputs
reg [7:0] mc;
reg [7:0] mp;
reg clk;
reg start;
// Outputs
wire [15:0] prod;
wire busy;
// Instantiate the Unit Under Test (UUT)
17. // Instantiate the Unit Under Test (UUT)
adder_32bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
#200 a=32'h66666666; b=32'h55555555;
#200 a=32'h00000000; b=32'h11111111;
#200 a=32'h98765432; b=32'hAAAAAAAA;
#200 a=32'h12121212; b=32'h21212121;
#200 a=32'h12345678; b=32'hF0000000;
// Add stimulus here
end
endmodule
25. output reg [7:0] out
);
always @(a,b)
out = a+b;
endmodule
SUBMODULE FOR SUB
module sub(
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
always @(a,b)
out = a-b;
endmodule
SUBMODULE FOR SHIFT
module shift(
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
always @(a,b)
out = b<<a;
26. endmodule
TESTBENCH
module main_tb;
// Inputs
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] d;
reg [7:0] e;
reg clk;
reg rst;
wire [7:0] out;
// Instantiate the Unit Under Test (UUT)
main uut (
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.clk(clk),
.rst(rst),
27. .out(out)
);
always
#200 clk = ~clk;
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
d = 0;
e = 0;
clk = 0;
rst = 1;
#200 rst = 0;
#400 rst = 1;
#200 a=8'h01; b=8'h02; c=8'h03; d=8'h04; e=8'h01;
#800 a=8'h08; b=8'h03;
#800 c=8'h03;
#800 d=8'h03;
#800 e=8'h04;
end
endmodule