1. EET 3350 Digital Systems Design
Textbook: John Wakerly
Chapter 8: 8.4
Counters
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2. Counters
• Counters
– Definition
– Types Count
– Characteristics Clock
Counter
• Asynchronous Counters
- 7490, 7492, 7493
optional inputs
• Synchronous Counters
• MSI Counters S1 S2
S3
– Especially the 74LS163 Sm
S4
• Counters in VHDL S5
• Other Counter Types
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3. Counters
• A counter is a circuit that produces a numeric
count each time an input clock pulse makes an
active transition
Clock Counter Count
Load an initial value, reset May also enable count,
to starting count, etc. select direction, etc.
optional inputs
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4. Counter
• From another viewpoint, a counter is any sequential
circuit whose state diagram is a single cycle
– in other words, counters are a special case of a finite state
machine
• Output is usually the state value, Moore machine
EN EN
RESET
EN
EN S2 EN
EN EN S1
S3
EN EN
Sm EN
S4
EN
EN S5 EN
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5. Counters
• Counters differ by a number of basic
characteristics, including:
Characteristic Description
Modulus Length of sequence
Coding Count sequence
Direction Up or down
Resetable Reset to zero
Loadable Load a specific value
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6. Counters
• Applications include:
Present State Next State
– system clock A B A B
0 0 0 1
– timer, delays 0 1 1 0
– watches, clocks, alarms 1 0 1 1
1 1 0 0
– counting events
– memory addressing
– frequency division 00 01
– sequence control
– cycle control
– protocols 11 10
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7. Counter Types
• Asynchronous • Modulus
– Ripple – Binary
• Synchronous – Decade
– Clocked – etc.
• Ring
000 • Johnson
– Twisted ring
101 001
• Up/Down
• Linear Feedback Shift-
100 010
Register Counter
011 (LFSR)
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9. Counters
• Modulus
– number of states in a counter’s cycle
• Given m states
– modulo-m counter or divide-by-m counter
• Power-of-2 counters use all states
• Non-power-of-2 counters have extra, unused
states
S1 S2
S3
Sm
S4
S5
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10. Example 4-bit Counters
• 4-bit Binary / Hex / Mod-16 Counter
– 0000, 0001, 0010, … 1110, 1111, 0000, 0001, …
all states used
• 4-bit BCD / Decade / Mod-10 Counter
– 0000, 0001, 0010, … 1000, 1001, 0000, 0001, …
six unused states
• 4-bit Ring Counter
– 1000, 0100, 0010, 0001, 1000, 0100, …
twelve unused states
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11. Counters
• Ripple counters
– asynchronous
– an n-state counter that is formed from n cascaded
flip-flops
– the clock input to each of the individual flip-flops,
with the exception of the first, is taken from the
output of the preceding one
– the count thus ripples along the counter's length
due to the propagation delay associated with each
stage of counting
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13. Ripple Counter Timing
• The ideal count sequence for the ripple
counter yields the timing diagram below
Q0 Q1 Q2 Q3
CLOCK
Q0
Q1
Q2
Q3
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14. Ripple Counter Timing
• But there is delay ( ∆ ) as shown below:
CLK
Q0
1∆
Q1
2∆
Q2
3∆
0 1 2 3 4
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15. Asynchronous Ripple Counter
Q0 divide-by-2
Q1 divide-by-4
a T flip-flop is a
natural frequency
divider …
Q2 divide-by-8
Q3 divide-by-16
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16. Decade and Binary CountersDM7490A
• The monolithic counter contains four masterslave flip-flops
• Gating to provide a divide-by-two counter and a three-stage binary
counter for which the count cycle length is divide-by-five.
• The counter has a gated zero reset and also has gated set-to-nine
inputs for use in BCD nine’s complement applications.
• To use the maximum count length (decade), the B input is connected
to
the QA output.
• The input count pulses are applied to input A and the outputs are as
described in the appropriate Function Table.
• A symmetrical divide-by-ten count can be obtained from the
counters by connecting the QD output to the A input and applying
the input count to the B input which gives a divide-by-ten square
wave at output QA.
18. Function Tables
BCD Count Sequence (Note 1) BCD Bi-Quinary (Note 2)
H = HIGH Level
L = LOW Level
X = Don’t Care
Note 1: Output QA is connected to input B for BCD count.
Note 2: Output QD is connected to input A for bi-quinary count
21. Logic Diagram
The J and K inputs shown without
connection are for reference only and
are functionally at a HIGH level.
22. SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92,
SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92,
SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
The three-stage binary counter has the count cycle length of
divide-by-five for the ’90, divide-by-six for the ’92, and divide-by-
eight for the ’93.
Logic Symbols
23. Function Tables
Count Sequence for ’92 Count Sequence for ’93
H = HIGH Level, L = LOW Level, X = Don’t Care
Note: Output QA is connected to input CKB.
26. Mod 11 counter using 7493
Clock CLK A
QA
CLK B
QB
7493
QC
R0(1)
QD
R0(2)
27. Synchronous Counters
• Asynchronous counters are easy to
understand, but avoid their use
– slow, limited by propagation delays
– error prone
• Characteristics of synchronous counters
– use a common clock pulse to trigger all flip-flops
simultaneously
– have a higher clock speed
– hardware is more complex but more reliable
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30. MSI Counters
• Counters can be built from individual SSI
Flip-Flops, e.g.,
– 7470
D1 D2
– 7474 and many others …
– 7479
• Counters may also be built using MSI
components
– 74x90, 74x92, 74x93
– 74x160, 74x161, 74x162, 74x163
– 74x168, 74x169
– 74x190, 74x191
we’ll look at this one
– 74x196, 74x197
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33. MSI Counter
• 74LS163 characteristics
– edge-triggered
– synchronously presettable
– cascadable
– count modulo 16 (binary) 74x163
• Synchronous Reset
(Clear) input that overrides
all other control inputs
– active only during the rising
clock edge
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