This whitepaper proposes novel VLSI design and verification strategies for 4G LTE /5G LTE-Advanced wireless technologies to meet the challenges like time-to-market in emerging wireless market in the telecom vertical.

1. NovelVLSIDesign&VerificationStrategiesfor
AdvancedWirelessTechnologies

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Abstract
Abbreviations
Markettrend/Challenges
Solution
BestPractices
CommonIssues
ConclusionConclusion
Reference
AuthorInfo
3
3
4
4
9
9
99
10
10
TableofContents

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RecentlytherehasbeenanincreaseintheusageofVLSIsolutionslikeFPGA/ASICinwirelesssystems,replac-
ingtheearlierusedDSPprocessors.NowmostoftheLayer1-PHYLayerisgettingdoneinFPGAtomeetthe
highbandwidth/throughputrequirements.ThisisbecauseDSPsavailableinthemarketarenotabletomeet
thecomplexityandtiming.AlsotheonlychoiceforDigitalIFProcessingFunctionisFPGAssincehighsampling
rateprocessingisnotpossibleinDSPs.Inthiswhitepaper,weproposenovelVLSIdesignandverification
strategiesfor4GLTE/5GLTE-Awirelesstechnologiestomeetthechallengesliketime-to-marketinemerging
wirelessmarketinthetelecom vertical.
Sl.No
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VLSI
FPGA
ASIC
DSP
LTE
LTE-ALTE-A
OFDMA
MIMO
FFT/iFFT
FEC
SV
DigitalIF
BFMBFM
GMAC
RTL
TTI
BTS
IO
VeryLargeScaleIntegration
FieldProgrammableGateArray
ApplicationSpecificIntegratedCircuit
DigitalSignalProcessors/Processing
LongTerm Evolution
LTE-AdvancedLTE-Advanced
OrthogonalFrequencyDivisionMultipleAccess
MultipleInputMultipleOutput
FastFourierTransform/InverseFastFourierTransform
ForwardErrorCorrection
System Verilog
Digitalintermediatefrequency
BusFunctionalModelBusFunctionalModel
GigaMultiplyAccumulates
RegisterTransferLevel
TransmissionTimeInterval
Basetransceiverstation
InputandOutput
FullFormAcronyms
Abstract
Abbreviations
NovelVLSIDesign&VerificationStrategiesforAdvancedWirelessTechnologies |3

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VLSIsolutionslikeFPGA/ASICcontinuetogainmomentum byfastreplacingtheearlierDSPprocessorsin
wirelesssystems.Thisisbecausehigh-endFPGAssupportalargenumberofembeddedDSPblocksleading
tooperationsatGMACswhoseorderofmagnitudearegreaterthantheperformanceofDSPsavailableinthe
market.ThecurrentleadingFPGAvendorsareXilinxandAltera.Forexample,Altera-StratixVGS(5SGSD8)
serieshave695KLogicElements,1050KRegisters,2567–M20KMemoryBlocksandvariableprecisionDSP
blockssupportingupto3,926-18x18multiplierswhichisequivalentto1,963DSPBlocks.Withthis,wecan
configureconfiguretonativelysupportsignalprocessingwithprecisionrangefrom 9x9to36x36includingfloat-
ing-pointimplementations[1]
.Xilinx–Vertex7serieshave2millionlogicgates,85MbblockRAMand3,600DSP
blocks[2]
.
Also,mostoftheLayer1-PHYLayerisgettingdoneinFPGAduetotheinabilityoftheavailableDSPstomeet
thehighbandwidth/throughputrequirements.FPGAsaremoresuitableforDigitalIFProcessingFunctionas
wellsincethehighsamplingrateprocessingisnotwellsupportedbytheDSPs.Thiswhitepaperproposes
novelVLSIdesignandverificationstrategiesfor4GLTE/5GLTE-Awirelesstechnologiestomeetthechallenges
liketimetomarketinemergingwirelessmarketintelecom vertical.
Timetomarketisakeyparameterwhichdeterminesthesuccessof4GLTE/5GLTE-Advancedwirelesstech-
nologiessystemsduetodemandingmarketcompulsionslikeshortlife-spanofsmartphones,tabletsand
otherdeviceswhichusethesewirelesstechnologies.ThesewirelesstechnologiesarebasedonMIMO-OFDMA
system[3]
andoptimalHW/SW partitioningforsuchMIMO-OFDMAsystem[4]
.TheHW portionofMIMO-OFDMA
needstobeimplementedonFPGA/ASICsusingVLSIdesign,developmentandverificationtechniques.The
gatecomplexityofthesedesignsisveryhighoftheorderof10Milliongates.Inthiswhitepaper,wepropose
somesomenovelVLSIdesign&verificationstrategiestomeetthetimetomarketrequirementforsuchhighcom-
plexityMIMO-OFDMAbasednextgenerationwirelesssystemsaslistedbelow.
Adoptingsystem leveldesignmethodology,insteadofbehavioralleveldesignmethodologyto
developFPGAprototype(proto)
AdoptingadvancedverificationtechniquesinPre-Silicon(Pre-Si)verificationinsteadofsimpleFile
I/Obasedtechnique
FPGAprototypinginparalleltoASICdevelopment
Post-siliconvalidationonFPGAprotoinparalleltoPre-Siverification
Markettrend/Challenges
Solution
NovelVLSIDesign&VerificationStrategiesforAdvancedWirelessTechnologies |4

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Thetraditionaldesignmethodologytoimplementthedigitalsignalprocessing(DSP)blocksinFPGA/ASIC
isbyusingbehaviorallevelofRTLcoding,whichisverytimeconsumingprocesstodeveloptheDSPblocks.
ItalsorequireshighlyskilledDSPexpertsanddesignengineersforimplementation.Eventhiscoding
methodologyactuallyevolvedfrom,switchlevelgateleveldataflow behaviorallevelabstractionof
hardwaredescriptionlanguage(HDL)developmentasdesigncomplexitybecamemorecomplexinthe
orderof10/100/1000/10000gatesrespectively.Asperthecurrentindustrytrends,behaviorallevelofRTL
codingcodingusedasthegatecomplexityismorethan10,000gateswhichisgenerallyreferredtoasVLSIdesign.
However,4G/5Gwirelesstechnologynecessitatesveryhighdesigncomplexityoftheorderof10Million
gates,hencetodevelopthesesystem onemorelevelofabstractioni.e.system levelofabstractionis
requiredintermsoftimetomarket,easytodesign,verificationandvalidation.
1.System LevelDesignMethodology
1.1TraditionalDesignMethodology
ForhighlycomplexsystemslikeBaseStations(BTS)for4G/5Gdevelopmentsystem,before goingtothe
ASICchipsetdevelopment,FPGAprototypingisnecessaryforproofofconcept.CurrentleadingFPGA
vendors,bothXilinxandAltera,provideaplatform forsystem leveldesign.
Altera-Altera-Qsys&MegacoreGUItool[1]
,haveDSP&IOinterfacefunctionlikeFFT/iFFT,FECblocks,Filters,CPRI,
Ethernet,DMA,RAM/ROM,FIFO,Arbiter,SerDes,PLLetc.Basicallyallthesystem designcomponentsare
availableintheAlteratoolitselfandthesecomponentsareeasilyinterconnectedwithAlteraproperty
interfacelikeAvalon®
–ST(streaming)andMM (MemoryMapped)interface.Byproperlyconfiguringand
interfacingthesereadymadeblocks(GUIbaseddraganddrop)inQsysdesignsystem console,wecan
easilybuildourownsystem andthiskindofdesignmethodologyisreferredassystem leveldesignmeth-
odology.odology.SomeDSPblockslikeTurbo/LDPCdecodersmaynotbeavailableintheAltera-Qsyslibrary,for
thisblockwecangeneratethedesignandtestbenchHDLcodeoutputfrom MATLABHDLCoder™tool
whichneedstobeusedinconjunctionwithMATLABSimulinktool.WecanmanuallywritetheHDL
wrapperandintegratewithQsyscomponentwhichisverylesstimeconsumingprocess.
Xilinx-Vivado™[2]
,designsuiteprovidesthecompleteSOCdesignplatform.Mostofthesystem design
modulesareavailableintheXilinxSmartCore™andLogiCORE™IPtoolitself.RTLcodeofDSPblockslike
turboencoder/decodercanbegeneratedfrom theVivadoHigh-LevelSynthesis(HLS)tool,whichconverts
theC/C++/System CdesigntoRTLdesign.EventhoughtheRTLcodeobtainedfrom thetool,itwillbe
betteroptimizedthanhandwrittenHDLcode.VivadoIPIntegratortoolprovidesGUIbasedplugandplay
componentswhichisinterconnectedbyAXIinterface,apartfrom thatFPGAitselfhavetheARMprocessor
whichwillprovidemoreelegantsolutions.
1.2System LevelDesignMethodology
NovelVLSIDesign&VerificationStrategiesforAdvancedWirelessTechnologies |5

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Thebenefitsofsystem leveldesignmethodologyare:
Hencethesystem leveldesignmethodologyiswellpredictableandthebestengineeringapproachfor
highlycomplexsystemslike 4G/5Gtechnologiesastheabovebenefitsleadtoquicktimetomarketsolu-
tions.
Reductioninthedesigncycletimedrastically
Reductioninthedesignengineerheadcount
Theseblocksareverifiedandvalidated,hencelowrisk
QuickFPGAprototyping,whichisproofofconceptforanynewsystem designidea/approach.
Lowcostproduct
2.AdvancedPre-SiVerificationStrategies
TheinputtestvectorsandexpectedoutputtestvectorsaregeneratedbyusingDSPalgorithmsreference
Matlab/Cmodel.BitaccuracycheckerinSystem VerilogcomparestheRTLblockoutputVsexpectedresult
andthisissimpleverificationmethodology.Thisstrategymaynotbeenoughtotestallthecornercases
andstresstestingofhighlycomplexsystem like4G/5Gwirelesssystems.
Figure1:TraditionVerificationStrategy
2.1TraditionalVerificationStrategy-FileI/OMethod
NovelVLSIDesign&VerificationStrategiesforAdvancedWirelessTechnologies |6

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InthisstrategyCmodeloftheDSPalgorithm needstobeintegratedwithSystem VerilogbyusingDPI
(DirectProgrammingInterface)techniqueortheMATLABmodeloftheDSPalgorithm needstobeinte-
gratedwithEDAsimulatorlinktool.Withthismethodology,wecangeneratethetestvectorontheflyand
wecanperform theconstrainedrandom unit/integration/regressionverificationmoreefficiently.Wecan
alsoverifythemagnitudeandphaseplotsagainsttheMATLABmodelautomatically.Aspartoftheregres-
sionverificationforfilters,functionaltestingisdonewiththefollowingtypeofinputvectors,impulse(for
latencyandgroupdelay),sine,stepforgain,multitoneandrandom vectors.
Figure2:AdvancedVerificationStrategy
2.2AdvancedVerificationStrategyusingC/MATLABreferencemodel
FPGAprototypeplatform isproofofconceptfortheideaanditisusefulforfunctionalvalidationhowever
withlower/reducedthroughputlevelsinceFPGAdesignrunsatlowerclockfrequencycomparedtoASIC.
TheadvantagesofFPGAproto-typingare:
DUT
Checker
(SV)
TestInput
Generation
(SV)
SVWrapper
(DP)
CCode
RealTimeWorkshop
(MatlabtoCconversion)
(Embedded)Matlab
FixedPointToolbox
SignalProcessing
Toolbox
System VerilogTest
Environment
ReferenceModel
(CCode)
3.FPGAPrototyping
NovelVLSIDesign&VerificationStrategiesforAdvancedWirelessTechnologies |7

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FPGAprototypingplatform helpfultovalidatethedriver-software.
Real/actualdatacanbeinjectedintothedesign,bywhichwecanidentifythemetastabilityissues,
simulationandsynthesismismatch.
RealHardware(CPRIandSerDes)canbevalidatedintheFPGAwhichwillbringupthefunctional
modelissues,ifany.
WeWecantestallpossiblerandom patterntestsequencegenerationinperiodicinterval(dai-
ly/weekly)tovalidateallthefeaturesoftheSOC.
Memorysize
Functionalvalidationunderextremethermalconditionsbyintensivelyheating
TimingandVoltageparametervalidation
Signalintegritytesttovalidatethecriticalsignalslikereset,clock,controlsignals,etc.,
ATPG(AutomaticTestPatternGeneration)whichwillinjectthetestvectorsintothechip
Hardwareinterfacetestlikeboarddiagnostictest-sanitycheck,poweredsignaltest
FrequencyclockmargintestFrequencyclockmargintest
LowVoltageVsLow/HighTemperaturetestandviceversa
Eyediagram,Timingmargin,Rise/Falltime,Jitter,BER–BitErrorRatiomeasurementtest
LoopbacktesttovalidatetheprotocollikeCPRI,Ethernet,etc.
Poweronresettest
NoiseImmunitytesttovalidatethenoisemargin
4.Post-SiliconValidation
PostSiliconValidationneedstobeperformedtogetherbymanufactureranddesignteam.Inthismethod-
ologywecantestallchipIOswithfullthroughput,whichwillverifyalltheDSPblocksthroughput,arbiter
speedandbus/bridgefunctionality.InFPGAproto-typingwewillhavethelimitationofspeedwhichwill
notbethereinpost-siliconvalidation.Wecanvalidatethefollowingfeaturesinpost-siliconvalidation:
Figure3:PostSiliconValidationStrategy
Chipset
(FPGA/ASIC-SOC)
PC
(Windows/LinuxPlatform)
ValidationEnvironment
TestGenerationHardware
(AutomaticTestingMachine)
NovelVLSIDesign&VerificationStrategiesforAdvancedWirelessTechnologies |8

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BestPractices
CommonIssues
Conclusion
Whentheproposeddesignandverificationstrategiesareadoptedcomparedtoothertraditionalstrate-
gies,therewillbedefinitebenefitsinthefollowing
1.Meetingthetiming:Itmeanssatisfyingthereal-timeprocessingrequirementsspecifiedinthe
standardwhichisTTIof1msforLTE.
2.Reliability:Sincetheproposedstrategiesensurereliabilitybymorethanonemeans,likepost-silicon
validationinadditiontopre-siverification,theoutcomeofthesestrategieswouldbehighlyreliable.
3.Scalability:Asthestandardsevolvemorefeatureswouldgetadoptedandduetoscalablenatureof
ourproposedstrategiesitcanbeeasilyadoptedfornewerversionsofthestandards.
4.TimetoMarket:4.TimetoMarket:Alltheproposedtechniques,ifusedeffectively,willgetadefiniteadvantageintimeto
marketcomparedtotraditionalstrategiesparticularlytheparallelpost-siliconvalidationonproto.
Althoughtheproposedstrategieshavedefinitebenefits,someofthechallengesintheproposedsolutions
maybe:
TheproposedVLSIdesign,verificationandvalidationstrategyisdefinitelyagoodapproachforLTE/LTE-A
Layer-1developmentascomparedtothetraditionalapproaches.Thissolutiongivesanedgeintimeto
marketwiththeflexibilityandrapidprototypingcapabilities,whichisacriticalparameterin4GLTE/5G
LTE-Advancedwirelesstechnologiessystemsduetotheshortlifespansofthedeviceswhichusethem.The
proposedstrategyalsoprovidesadditionalbenefitsofmeetingthetiming,reliabilityandscalability.
1.Requiresachangeinmindsetoftheengineerstoadapttheproposedstrategiescomparedtotradi
tionalstrategies
2.Toolcostforadoptingsomeoftheproposedstrategiesishighercomparedtotraditionalstrategies
NovelVLSIDesign&VerificationStrategiesforAdvancedWirelessTechnologies |9

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CSaminathan
HCLEngineeringandR&DServices
GSangeet
HCLEngineeringandR&DServices
DrGVRangaraj
HCLEngineeringandR&DServices
Reference
AuthorInfo
1.AlteraFPGAandTools-http://www.altera.com
2.XilinxFPGAandTools-http://www.xilinx.com
3.3GPPLTEStandards:TS36.201,TS36.211&TS36.212
http://www.3gpp.org/ftp/Specs/html-info/36201.htm
http://www.3gpp.org/ftp/Specs/html-info/36211.htm
http://www.3gpp.org/ftp/Specs/html-info/36212.htm
4.Altera’sWhitepaperonDSP-FPGASystemPartitioningforMIMO-OFDMAWirelessBasestations,October20074.Altera’sWhitepaperonDSP-FPGASystemPartitioningforMIMO-OFDMAWirelessBasestations,October2007
AdoptingthePairwiseTestDesignTechniquetoOptimizePrinterDriverTestCoverage |10