The document discusses the 8086/8088 microprocessors. It describes their basic features, including being 16-bit microprocessors introduced in 1978/1979 and using HMOS technology. It also covers their pin configurations and diagrams, addressing modes, minimum and maximum modes, and descriptions of the various pins and signals.

1. 8086/8088 Microprocessor
Introduction to the processor and its
pin configuration

2. Topics
• Basic Features
• Pinout Diagram
• Minimum and Maximum modes
• Description of the pins

3. Basic Features
• 8086 announced in 1978; 8086 is a 16 bit
microprocessor with a 16 bit data bus
• 8088 announced in 1979; 8088 is a 16 bit
microprocessor with an 8 bit data bus
• Both manufactured using High-performance
Metal Oxide Semiconductor (HMOS)
technology
• Both contain about 29000 transistors
• Both are packaged in 40 pin dual-in-line
package (DIP)

4. 8086/8088 Pinout Diagrams
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
HOLD
HLDA
WR
M/IO
DT/R
DEN
ALE
INTA
TEST
READY
RESET
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0
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
8086 32
31
30
29
28
27
26
25
24
23
22
21
GND
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
A15
A16/S3
A17/S4
A18/S5
A19/S6
SS0
MN/MX
RD
HOLD
HLDA
WR
IO/M
DT/R
DEN
ALE
INTA
TEST
READY
RESET
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11
12
13
14
15
16
17
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19
20
40
39
38
37
36
35
34
33
8088 32
31
30
29
28
27
26
25
24
23
22
21
BHE has no meaning on the 8088
and has been eliminated

5. Multiplex of Data and Address Lines in
8088
• Address lines A0-A7 and
Data lines D0-D7 are
multiplexed in 8088.
These lines are labelled as
AD0-AD7.
– By multiplexed we mean
that the same pysical pin
carries an address bit at
one time and the data bit
another time
GND
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
A15
A16/S3
A17/S4
A18/S5
A19/S6
SS0
MN/MX
RD
HOLD
HLDA
WR
IO/M
DT/R
DEN
ALE
INTA
TEST
READY
RESET
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10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
8088 32
31
30
29
28
27
26
25
24
23
22
21

6. Multiplex of Data and Address Lines in
8086
• Address lines A0-A15 and Data lines D0-D15 are
multiplexed in 8086. These lines are labelled as
AD0-AD15.
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
HOLD
HLDA
WR
M/IO
DT/R
DEN
ALE
INTA
TEST
READY
RESET
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10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
8086 32
31
30
29
28
27
26
25
24
23
22
21

7. Minimum-mode and Maximum-mode
Systems
• 8088 and 8086 microprocessors can be
configured to work in either of the two
modes: the minimum mode and the
maximum mode
 Minimum mode:
 Pull MN/MX to logic 1
 Typically smaller systems and contains a
single microprocessor
 Cheaper since all control signals for
memory and I/O are generated by the
microprocessor.
 Maximum mode
 Pull MN/MX logic 0
 Larger systems with more than one
processor (designed to be used when a
coprocessor (8087) exists in the system)
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
HOLD
HLDA
WR
M/IO
DT/R
DEN
ALE
INTA
TEST
READY
RESET
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0
11
12
13
14
15
16
17
18
19
20
40
39
38
37
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8086 32
31
30
29
28
27
26
25
24
23
22
21
Lost Signals in
Max Mode

8. Minimum-mode and Maximum-mode
Signals
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
QS0
QS1
TEST
READY
RESET
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10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
8086 32
31
30
29
28
27
26
25
24
23
22
21
Max Mode
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
HOLD
HLDA
WR
M/IO
DT/R
DEN
ALE
INTA
TEST
READY
RESET
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10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
8086 32
31
30
29
28
27
26
25
24
23
22
21
Min Mode
Vcc GND

9. 8086 System Minimum mode
C l o c k
g e n e r a t o r
A E N 2
A E N 1
8 0 8 6 C P U F / C
+ 5 V
R E S
W a i t - S t a t e
G e n e r a t o r
C L K
R E A D Y
R E S E T
M / I O
I N T A
R D
W R
P C L K
M N / M X + 5 V
S T B
O E
8 2 8 2
L a t c h
A L E
A D 0 - A D 1 5
A 1 6 - A 1 9
A 0 - A 1 9
A d d r e s s B u s
B H E B H E
D 0 - D 1 5
8 2 8 6
D T / R
D E N
T
O E
1 6
C o n t r o l
B u s

10. B u s C o n t r o l le r 8086 System Maximum Mode
8 0 8 6 C P U
C lo c k
g e n e r a t o r
W a it - S t a t e
G e n e r a t o r
C L K
R E A D Y
R E S E T
M N / M X
A L E
S T B
O E
8 2 8 2
L a t c h
A 0 - A 1 9
A d d r e s s B u s
A D 0 - A D 1 5
A 1 6 - A 1 9 B H E
+ 5 V
R E S
S 0
S 1
S 2
C L K
S 0
S 1
S 2
D A T A
8 2 8 6
T
O E
T r a n s c e i v e r
G n d
D E N
D T / R
M R D C
M W T C
A M W C
I O R C
I O W C
A I O W C
I N T A
8 2 8 8

11. Description of the Pins
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
RQ/GT0
RQ/GT1
LOCK
S2
S1
S0
QS0
QS1
TEST
READY
RESET
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10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
8086 32
31
30
29
28
27
26
25
24
23
22
21
Max Mode
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
BHE/S7
MN/MX
RD
HOLD
HLDA
WR
M/IO
DT/R
DEN
ALE
INTA
TEST
READY
RESET
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10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
8086 32
31
30
29
28
27
26
25
24
23
22
21
Min Mode
Vcc GND

12. RESET Operation results
CPU component Contents
Flags Cleared
Instruction Pointer 0000H
CS FFFFH
DS, SS and ES 0000H
Queue Empty

13. AD0 - AD15: Address Data Bus
AD0 – AD15 Address
Data

14. A17/S4, A16/S3 Address/Status
A17/S4 A16/S3 Function
0
0 Extra segment access
0
1 Stack segment access
1
0 Code segment access
1 1 Data segment access

15. A19/S6, A18/S5 Address/Status
A18/S5: The status of the
interrupt enable flag bit is updated
at the beginning of each cycle. The status of the flag
is indicated through this pin
A19/S6: When Low, it indicates that 8086 is in
control of the bus. During a "Hold acknowledge"
clock period, the 8086 tri-states the S6 pin and thus
allows another bus master to take control of the
status bus.

16. S0, S1 and S2 Signals
S2 S1 S0 Characteristics
0 0 0 Interrupt
acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive State

17. QS1 and QS2 Signals
QS1 QS1 Characteristics
0 0 No operation
0 1 First byte of opcode from queue
1 0 Empty the queue
1 1 Subsequent byte from queue

18. Read Write Control Signals
IO/M DT/R SSO CHARACTERISTICS
0 0 0 Code Access
0 0 1 Read Memory
0 1 0 Write Memory
0 1 1 Passive
1 0 0 Interrupt Acknowledge
1 0 1 Read I/O port
1 1 0 Write I/O port
1 1 1 Halt

19. 8086 Memory Addressing
Data can be accessed from the memory in four
different ways:
• 8 - bit data from Lower (Even) address Bank.
• 8 - bit data from Higher (Odd) address Bank.
• 16 - bit data starting from Even Address.
• 16 - bit data starting from Odd Address.

20. Treating Even and Odd Addresses
H ig h e r
A d d r e s s
B a n k
( 5 1 2 K x 8 )
O D D
L o w e r
A d d r e s s
B a n k
( 5 1 2 K x 8 )
E V E N
A 1 - A 1 9
A d d r e s s B u s
D a ta B u s ( D 0 - D 1 5 )
B H E A 0
D 8 - D 1 5 D 0 - D 7

21. 8-bit data from Even address Bank
A 1 - A 1 9
D 0 - D 1 5
B H E = 1
D 8 - D 1 5 D 0 - D 7
x
x + 2
x + 4
A 0 = 0
x + 1
x + 3
x + 5
O d d B a n k E v e n B a n k
MOV SI,4000H
MOV AL,[SI+2]

22. 8-bit Data from Odd Address Bank
A 1 - A 1 9
D 0 - D 1 5
x
x + 2
O d d B a n k E v e n B a n k
x + 1
x + 3
B H E = 0 A 0 = 1
D 8 - D 1 5
D 0 - D 7
MOV SI,4000H
MOV AL,[SI+3]

23. 16-bit Data Access starting from Even Address
A 1 - A 1 9
D 0 - D 1 5
O d d B a n k E v e n B a n k
B H E = 0
x
x + 2
A 0 = 0
x + 1
x + 3
D 8 - D 1 5
D 0 - D 7
MOV SI,4000H
MOV AX,[SI+2]

24. 16-bit Data Access starting from Odd Address
A 1 - A 1 9
O d d B a n k E v e n B a n k
D 8 - D 1 5
D 0 - D 7
A 1 - A 9
0 0 0 5
0 0 0 7
0 0 0 9
0 0 0 4
0 0 0 6
0 0 0 8
A 1 - A 1 9
O d d B a n k E v e n B a n k
D 8 - D 1 5
D 0 - D 7
A 1 - A 9
0 0 0 5
0 0 0 7
0 0 0 9
0 0 0 4
0 0 0 6
0 0 0 8
( a ) F ir s t A c c e s s fr o m O d d A d d re s s ( b ) N e x t A c c e s s fr o m E v e n A d d r e s s
MOV SI,4000H
MOV AX,[SI+5]

25. T 1 T 2 T 3 T w a i t T 4
C L K
A D 0 - A D 1 5
B H E
A L E
S 2 - S 0
M / I O
R D
R E A D Y
D T / R
D E N
W R
Read Timing Diagram

26. Write Machine Cycle

27. INTR (input)
Hardware Interrupt Request Pin
• INTR is used to request a hardware interrupt.
• It is recognized by the processor only when IF =
1, otherwise it is ignored (STI instruction sets this flag bit).
• The request on this line can be disabled (or
masked) by making IF = 0 (use instruction CLI)
• If INTR becomes high and IF = 1, the 8086
enters an interrupt acknowledge cycle (INTA
becomes active) after the current instruction has
completed execution.

28. For Discussion
• If I/O peripheral wants to interrupt the
processor, the “interrupt controller” will send
high pulse to the 8086 INTR pin.
• What about if a simple system to be built and
hardware interrupts are not needed;
What to do with INTR and INTA?

29. NMI (input) Non-Maskable
Interrupt line
• The Non Maskable Interrupt input is similar to
INTR except that the NMI interrupt does not
check to see if the IF flag bit is at logic 1.
• This interrupt cannot be masked (or disabled)
and no acknowledgment is required.
• It should be reserved for “catastrophic” events
such as power failure or memory errors.

30. 8086 External Interrupt Connections
NMI - Non-Maskable Interrupt INTR - Interrupt Request
Interrupt Logic
int into
Divide
Error
Single
Step
NMI Requesting
Device
8086 CPU Intel
8259A
PIC
NMI
INTR
Software Traps
Programmable
Interrupt Controller
(part of chipset)

31. TEST (input)
• The TEST pin is an input that is tested by the
WAIT instruction.
• If TEST is at logic 0, the WAIT instruction
functions as a NOP.
• If TEST is at logic 1, then the WAIT instruction
causes the 8086 to idle, until TEST input
becomes a logic 0.
• This pin is normally driven by the 8087 co-processor
(numeric coprocessor) .
• This prevents the CPU from accessing a memory
result before the NDP has finished its calculation

32. Ready (input)
• This input is used to insert wait states into
processor Bus Cycle.
• If the READY pin is placed at a logic 0 level,
the microprocessor enters into wait states and
remains idle.
• If the READY pin is placed at a logic 1 level, it
has no effect on the operation of the processor.
• It is sampled at the end of the T2 clock pulse
• Usually driven by a slow memory device

33. 8284 Connected to 8086 Mp
Ready
CLK
Reset
+ 5 V
R
C
RES
X1
X2
F/C
RDY1
RDY2
8284
AEN1
AEN2
RESET KEY
por ci M 6808

34. HOLD (input)
• The HOLD input is used by DMA controller to
request a Direct Memory Access (DMA) operation.
• If the HOLD signal is at logic 1, the microprocessor
places its address, data and control bus at the high
impedance state.
• If the HOLD pin is at logic 0, the microprocessor
works normally.

35. HLDA (output)
Hold Acknowledge Output
• Hold acknowledge is made high to indicate to
the DMA controller that the processor has
entered hold state and it can take control over the
system bus for DMA operation.

36. DMA Operation