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Introduction
[object Object],[object Object],[object Object],[object Object]
Bit = binary digit : 0/1 Program(S/W) A sequence of instruction S/W = Program + Data » The data that are manipulated by the program constitute the data base Application S/W = DB, word processor, Spread Sheet System S/W = OS, Firmware, Compiler, Device Driver
Digital Components ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
AND Gate
 
OR Gate
 
 
 
 
Boolean Algebra ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Boolean Algebra ,[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
 
 
 
De Morgan’s law
 
Boolean Algebra Rule
Karnaugh Map ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Map
F = x + y’z
Adjacent Square Number of square = 2n (2, 4, 8, ….) The squares at the extreme ends of the same horizontal row are to be considered adjacent The same applies to the top and bottom squares of a column  The four corner squares of a map must be considered to be adjacent Groups of combined adjacent squares may share one or more squares with one or more group
 
Half Adder Logic Diagram Truth Table A  half adder  adds two one-bit binary numbers  A  and  B . It has two outputs,  S  and  C .  The simplest half-adder design, pictured on the right, incorporates an  XOR gate  for  S  and an  AND gate  for  C . Half adders cannot be used compositely, given their incapacity for a carry-in bit.
Full Adder A  full adder  adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as  A ,  B , and  C in ;  A  and  B  are the operands, and  C in  is a bit carried in. A full adder can be constructed from two half adders by connecting  A  and  B  to the input of one half adder, connecting the sum from that to an input to the second adder, connecting  C in  to the other input and OR the two carry outputs  Logic Diagram Truth Table
SR Flip-Flop Graphic Symbol Truth Table A  SR flip-flop  has three inputs, S (for  set ), R (for  reset ) and C (for  clock ). It has an output Q. The  undefined condition  makes the SR flip-flop difficult to manage and therefore it is seldom used in practice.
D Flip-Flop Graphic Symbol Truth Table The D flip-flop is a slight modification of the SR flip-flop by inserting an inverter between S and R and assigning the symbol D to the single input. If D=1, the output goes to the state 1, and if D=0, the output of the flip flop goes to the 0 state.
JK Flip-Flop Graphic Symbol Truth Table Inputs J and K behave like inputs S and R. When inputs J and K are both equal to 1, a clock transition switches the output of the flip-flop to their complement state.
T Flip-Flop Truth Table Graphic Symbol The T flip-flop is obtained from a JK flip-flop when inputs J and K are connected to provide a single input designated by T. The flip-flop thus has only two conditions.
Excitation Tables  During the design of circuits, we need a table that lists the required input combinations for a given change of state. Such  table is called a flip flop  excitation table.
Sequential Circuits ,[object Object],Example of a Sequential Circuit Ax Bx Ax+Bx A’x x’ A+B (A+B).x A=Ax+Bx,  B=A’x y=(A+B).x State Table

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Introduction

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  • 3. Bit = binary digit : 0/1 Program(S/W) A sequence of instruction S/W = Program + Data » The data that are manipulated by the program constitute the data base Application S/W = DB, word processor, Spread Sheet System S/W = OS, Firmware, Compiler, Device Driver
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  • 22. Map
  • 23. F = x + y’z
  • 24. Adjacent Square Number of square = 2n (2, 4, 8, ….) The squares at the extreme ends of the same horizontal row are to be considered adjacent The same applies to the top and bottom squares of a column The four corner squares of a map must be considered to be adjacent Groups of combined adjacent squares may share one or more squares with one or more group
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  • 26. Half Adder Logic Diagram Truth Table A half adder adds two one-bit binary numbers A and B . It has two outputs, S and C . The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C . Half adders cannot be used compositely, given their incapacity for a carry-in bit.
  • 27. Full Adder A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A , B , and C in ; A and B are the operands, and C in is a bit carried in. A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting C in to the other input and OR the two carry outputs Logic Diagram Truth Table
  • 28. SR Flip-Flop Graphic Symbol Truth Table A SR flip-flop has three inputs, S (for set ), R (for reset ) and C (for clock ). It has an output Q. The undefined condition makes the SR flip-flop difficult to manage and therefore it is seldom used in practice.
  • 29. D Flip-Flop Graphic Symbol Truth Table The D flip-flop is a slight modification of the SR flip-flop by inserting an inverter between S and R and assigning the symbol D to the single input. If D=1, the output goes to the state 1, and if D=0, the output of the flip flop goes to the 0 state.
  • 30. JK Flip-Flop Graphic Symbol Truth Table Inputs J and K behave like inputs S and R. When inputs J and K are both equal to 1, a clock transition switches the output of the flip-flop to their complement state.
  • 31. T Flip-Flop Truth Table Graphic Symbol The T flip-flop is obtained from a JK flip-flop when inputs J and K are connected to provide a single input designated by T. The flip-flop thus has only two conditions.
  • 32. Excitation Tables During the design of circuits, we need a table that lists the required input combinations for a given change of state. Such table is called a flip flop excitation table.
  • 33.