VLSICS Design

vlsi circuits vlsi design reliability computer-aided design (cad) post-cmos vlsi wireless communications emerging technologies testing vlsi applications design fault-tolerance molecular security low power and power aware design low power sensor networks video nano electronics biological and quantum computing intellectual property creating and sharing communication systems fpga vlsi cmos vlsi applications (communications communications phd leakage power wireless wireless networks full adder phdstudent sram soc etc) reversible logic design vlsi circuits computer-aided design (cad) l dsp pattern recognition biological and quantum computing intellectual prop etc) nano electronics fault-tolerance emerging technologies post-cmos vl finfet pipeline high speed digital image processing visualization image processing xilinx analog testing digital signal processing (dsp) transistor stacking image formation communication iir fir vlsi circuit simulation write delay biological and quantum computing * intellectua etc) * nano electronics fault-tolerance * emerging technologies * design * vlsi circuits * computer-aided design matlab low-power power gating static random access memory delay noise figure dibl analog-to-digital converter leakage current universal verification methodology (uvm) power dissipation sleep transistor static noise margin read delay assist circuitry single-port nanotechnology power management verilog adiabatic logic adc nanoelectronics 45nm technology low power. dual threshold design reverse body bias standby power voltage control circuit power consumption garbage output lna dram domino logic adaptive biasing cryptography quantum computing pass transistor logic low power design low voltage dynamic power network on chip floating gate mosfet mosfet vlsi researcher research lattice networks formal symmetrization concurrent computing carbon nano-apex emission regularity complementary metal oxide semiconductor multimedia embedded systems mips risc processor spartan3e frequency range control voltage generator integrator dcc motion estimation hevc dsp processing kogge stone adder roba architecture high speed multiplier error analysis efficient approximate computing accuracy embedded rams back gate biasing. spi master core reusable vip questasim functional verification snm segmentation mtncl asynchronous voltage stacking standby start-up circuit hspice cntfet mri reversible gate transistor modeling. carry save adder (csa) gate diffusion input (gdi) sub threshold leakage link training and status state machine (ltssm) universal serial bus (usb) synthesizable active agent functional coverage uvm(universal verification methodology) axi(advanced extensible interface) amba(advance microcontroller bus architecture) ahb2apb stepwise charging adiabatic ber network-on-chip register exchange method traceback method simulink quantum dot sensors power delivery pacemaker impalntablr bio-medical devices energy harvesting security. testability scan-based attack fault injection side-channel analysis hardware security vlsi technology phase locked loop (pll) quaternary logic adiabatic logic. voltage scaling ecu scheduling oem dynamic gesture recognition implicit interaction edge point sequential extraction least-squares method context information very large scale integration (vlsi). slack based genetic algorithm sub-threshold circuits quantum cost eeg power gain carbon nanotube field effect transistor operational amplifier transconductance slew rate amplifier power dissipation. rf cmos flip-flop alu crosstalk current mirror journalism machine learning artificial intelligence vlsi communication télécommunications signal routing data compression random access scan design for test error rate approximate computing (ac) technology watermarking analog and mixed-signal signal identification face recognition audio/speech processing and coding mimo layout congestion concurrency lattice network field emission concurrent processing carbon nano-apex signal image coding and compression image segmentation computer vision • visualization mimo. analog and mixed signal processing emd imf brent kung adder parallel prefix adders sum of absolute difference synthesis power delay product (pdp) multiplier cmos vlsi state retention average power noc * vlsi applications short channel effects (sces) bus encoding vhdl ripple carry adder work function cdma gds format. ddc file fifo hol blocking virtual output queuing 2d mesh 32nm technology sram cell through silicon via. three dimensional integration peak temperature hotspot 12-t sram cell body effect bota ota bulk-driven mos tsmc multi-vdd application specific integrated circuit digital up-counter digital down-counter power line carrier communication edge detection xilinx system generator state dependent spare cell eco cell engineering change order (eco) rtl. stuck-at fault fault simulation fault coverage automatic test pattern generation (atpg) exclusive-nor (xnor) exclusive-or (xor) garbage nios-ii soft processor deblocking filter nmos & pass transistor. fredkin gate feynman gates resonant tunneling diode (rtd) molecular electronics logic circuits etc channel. amba snm and process variations. vlsi architecture lifting scheme ofdm dwt fft islip scheduler on-chip routing switch system-on-chip zigzag quantization jpeg thin film transistor tft. poly-thiophene pt transmission gate logic deep submicron regime corner angle concave corner grooved mosfet planar mosfet hybrid register exchange method cmfb 1.5 bit stage hybrid system fast fourier transform (fft) fault dictionary fault diagnosis encoding cmos inverter cad low power consumption itrs high performance (hp) overlap underlap triple gate double gate search based memory key pipelining aes pipelining static and dynamic mac coulomb oscillation coulomb blockade single-electron transistor primitive characteristic polynomial bist misr lfsr field programmability floating gate fet square wave generator reversible parallel binary adder/subtractor. garbage input/output test minimization. heuristic approach fault library adaptive scheduled fault detection mos resistor linear range wilson mirror bulk-input neighbor aps trajectory of mn gps (global positioning system) ieee 802.11 photovoltage photodetectors schottky junction optoelectronics lut & sdr gsm bram asic voltage-controlled oscillator (vco) modulo-n addition and multiplication multiple-valued logic quality of service. wide band code division multiple access call admission control current substractor. opamp mix-column sub-channel advanced encryption standard sub-threshold bio-medical kogge-stone adder offset quadrature phase shift keying modulator and symbol-to-chip bit-to-symbol cyclic redundancy check min quaternary voltage mode multiple-valued logic (mvl) noise shaping autosar snr temperature-insensitive high performance vlsi circuits voltage control multicore digital-to-analog converter enob encoder dtmos low power circuit asynchronous design power hardware description language (hdl) discrete wavelet transform (dwt) fault. rfid return losses nsga-ii algorithm cnt high performance & power delay product n-bit reversible comparator inventive gate constant input full subtractor stability multism bipolar junction transistor fabrication 4tdram 3tdram 3t1d dram library free synthesis on the fly mapping critical path cell re-ordering recycling folded cascode lock range oscillator injection-locked clock and data recovery eye diagram high vth low vth dynamic threshold active mode leakage reduction minimum leakage vector (mlv) standby mode band to band tunneling (btbt) dynamic range single precision instruction set analog multiplexer pass transistors current mode logic microcontroller gdi pae speed subthreshold virtual channel elastic buffer virtual allocator phase frequency detector gate diffusion cell voltage controlled oscillator charge pump. trans - conductance. polarization algan/gan modfets drain - conductance cut-off frequency regulated cascode low-voltage & low-power molecular communication nano networks diffusion channel channel capacity rf dc optical illumination ac privacy university articles journals vlsics call for papers mobile networks real time system middleware embedded architecture education wireless sensor network graphic design web design electronics noise margin hdl uvm sv argument elaboration compilation precompilation * wireless communications * post-cmosvlsi * design post-cmosvlsi mobile singal processing v a back gate biasing * low power acceptance probabi circuit metrics error metrics mean error distance acceptance probabilit data stucture database data mining information * post-cmos vlsi * wireless communications high power iterative symmetry decompositi built in self-repair (bisr) memory built in self-test (mbi storage and retrieval internet of things technology implementation array signal processing discrete cosine transform (dct intellectual property creating radio frequency identification organic thin film transistors positive feed back memoryless hrem hybrid register exchange metho algorithm redundancy bit removal formal methods in conformance opencircuit fault. nonlinear signals and systems signal and image processing signal processing leakage power and switching probability. pass transistor logic. bme gate detection and estimation of signal parameters data mining techniques digital & mobile signal processing 3d and surface reconstruction face recognition & super-resolution imaging pattern recognition and analysis image acquisition & medical image processing variable threshold mos inverter noise-margin propagation delay dynamic threshold mos inverter sub- threshold computer graphics and visualization image and video processing & analysis coding and transmission galois addition and multiplication. co-ordinate evaluation multimedia systems and devices design of experiments statistical modelling process variations ft combinationalcircuits minimum transition register exchange method. digital clock manager nano-apex emission. iterative symmetry decomposition regularity. brent kung adder. symmetric function. max quaternary current mode symmetric function nano-technology. verilog a vlsi design & communication systems multi threshold. forward body bias shape representation • object detection networks • communication • motion detection remote sensing biomedica mixed signal processing • data mining techniques • video signal processing • distributed source coding • dsp implementation • multi-view geometry surface reconstruction • face recognition • image segmentation digital clock manager. • depend3d and stereo imaging • image acquisition & medical image processing • p • image acquisition & medical image processing adaptive filters filter design and structures face and gesture nano scale electronic design and applications inverse. inhibition implication equivalence exclusive -or computer-aided design (cad compressed code systems. arithmetic coding bus transition reduction low power vlsi branch-and- bound fine-grained dvs pareto-optimal atpg iscas compaction test vector coarse-grained fabric reconfigurable architecture domain-specific architecture reconfigurable computing data synchronization ternary tree network gals binary field. prime field crypto processor leakage current. gate oxide tunneling subthreshold leakage dual-threshold multiple error correction. multiple error detection matrix codes error correction codes memory testing mbms mbsfn pcfich pdsch pdcch pmch pbch logic gates cntfet technology minority function logic optimization state encoding synthesis constraints fsm optimization zero padding. fast fourier transform reduced switching activity 2-d bypass multiplier column bypass multiplier low power multipliers rtl schematic navigation future computing. partial products toffoli gates reversible logic gates uvm-ml. verification abstraction layer(val) virtual register interface (vri) incisive software extension (isx) ip-xact register and memory model universal verification component(uvc) video data interface(s) register interface(s) system verilog memory effect opamp sharing analog to digital converter (adc) extended xy on-chip communication diametrical 2d mesh routing noc routing low pass filter (lpf) charge pump (cp) voltage controlled oscillator (vco) divider (div) true signal phase clock (tspc) phase frequency detector (pfd) delayed flip-flop (d-ff) vcg & merging. manhattan routing model channel routing track tlg threshold spice rtd lphs (low power high speed). diode based logic split-level energy recovery two phase clocked 3-d sentaurus tcad tool. subthreshold slope short channel effect silicon-on-insulator(soi) high k gate oxide tg finfet gate all around(gaa) biological and quantum computing intellectual pro etc) nano electronics fault-tolerance emerging technologies post-cmos design vlsi circuits computer-aided design (cad) total harmonic distortion noise spectral density gilbert cell tcad sub threshold slope
soi finfets sces process and device simulation fringing field cylindrical surround gate (csg) mosfet barrier lowering precharge pulse dynamic circuit buffer traditional march tests. complexity concurrent technique modified march c- algorithm march c- swsfets multi-channel sub-micron regimes. stand-by leakage power svl circuit 10 transistor serf adder delay calculation logical effort multiplexer based adders adder topologies technology independent mapping medical imaging signal skew simultaneous switching equal / unequal rise time switching activity cic decimation filter oversampling discrete time sigma delta modulation apa aca uwb mc-cdma scs fixed point reduced bit precision pipeline architecture field-programmable gate-array (fpga) lifting based scheme dvs meta-stability detector cmos transmission logic razor encryption vhdl code mixcolumn aes bus enhanced noc. routing algorithm deadlock detection deadlock recovery layout design. power delay product low- power logic devices pass logic implementations adders spurious power suppression technique digital signal processing radix -2 modified booth algorithm average power dissipation carry look ahead adder carry skip adder constant inputs and proposed fault tolerant full a proposed parity preserving gate router walsh code center frequency of oscillation phase noise integrated circuit (ic) cmos ring oscillator (ro) analog and mixed signal (ams) low power full adder carbon nano-tube field effect transistor carbon nano-tube full adder & vlsi. pdp ptl biological basic gates. full-adder cell cnfet silicon-on-insulator schmitt-triggered delay-insensitive asynchronous logic ultra-low voltage back propagation algorithm neural network architecture back gatebiasing. very large scale integrated (vlsi)circuits xor-xnor circuit hybrid full adder cordic algorithm gabor algorithm medical image vlsi circuits computer-aided design (cad) low powe sub-threshold region ultra low power threshold voltage (vt) independent-gate (ig) gate workfunction dual-metal gate (dmg) rf switch wireless network radio-frequency low noise amplifier advanced design system image compression. vlsi architectures lifting schemes discrete wavelet transform corrector. detector decoder double edge triggered(det ) d flipflop(dff ) ring-counter gated-clock first-in–first-out (fifo) gc-element analog to digital converter. fat tree tc-bc encoder tiq wishbone interface wishbone bus soc buses phase detector loop filter adpll dco reversibility miniaturization analog multipliers analog integrated circuits carbon nanotube fet data weighted averaging dynamic element matching bandpass σ∆ modulator sigma delta modulation over sampling tmr virtuoso cadence write-ability read stability n-curve interconnects coupling fpga spartan 3 development board vending machine fsm biological and wireless communications bus-invert inductance effects rsa. modular multiplication sign estimation technique sign detection carry-save adder efficient architecture carry select adder. carry increment adder carry save adder input third order intercept point (iip3) shunt-series peaking dual source degenerated current reuse stacking technique self cascode folded cascode ota meter count efficiency loom machine moore’s law. gain trans-conductance silvaco tcad tool dmg mosfet gate leakage sram and vlsi. cmos logic hysteresis. current comparator current mode static ram (sram) carbon nanotube field-effect transistor (cntfet) key generation elliptic curve cryptography mud bit/block errors. memory section addressing progressive coding memory fault transmission gates stacking effect process technology parasitic fringe capacitance. hetero-gate band-to-band tunnelling keywords sram leakage power and switching probability bme gate. power saving capacitance[5] mealy and moore machines fsm decomposition [2] nanowire mosfet. interface traps hot carrier effect fixed charges channel length modulation atlas-3d crossbar routing virtex – 6 low power. virtex-5 virtex-4 verilog hdl truncated multiplier spartan-3e fast addition field programmable gate array (fpga) channel mba snm and process variations linearity gate stack dg-tfet analog effective thermal conductivity fine mesh(fm) coarse mesh(cm) heat sink source point target point integrated circuits continuous domain floorplaning hotspots 3d chips corba merit factor polyphase sequence quaternary sequence ternary sequence pulse compression psrr temperature coefficient bgr synthesis. discrete cosine transform (dct) radio frequency identification rfid organic thin film transistors otft serf adder positive feed back adiabatic logic memoryless hrem. redundancy bit removal algorithm analog and mixed-signal circuit formal methods in conformance testing opencircuit fault forbidden pattern free micron coupling capacitance parasitic flash adc xor gate based encoder bridge full adder. hybrid xor-xnor circuit very large scale integrated (vlsi) circuits power-delay product (pdp) moscap dynamic circuits majority-not gate pseudo nmos dual rail domino logic static cmos logic comparator. interval arithmetic floating-point wireless application. rf design low noise amplifier (lna) 90nm technology bics iddq testing resistive path short (bridging) defect operational amplifier (op amp) nano-cmos technology areaoptimization. power ooptimization turbo decoder turbo encoder single/multiple input signature register linear feedback shift register tool computer-aided design test bist generator multiple outputs high performance voltage-controlled oscillator (vc phase-locked loop (pll) eda tool. vco baseband pll charge pump pll pll redundancy hardware controller fault tolerance high frequency current buffer compensation cmos analog circuit mobility & mole fraction. drain current channel thickness biaxial strained flash analog to digital converter sampling switch peak power track and hold circuit scan chain. latch test time double edge triggered flipflop scanflop carbon nanotube mulitple valued logic vlsi. combinational circuits co-ordinate evaluation. galois addition and multiplication multi vth swing limited interconnect circuit boostable repeater buffer insertion delay stages time to digital converter (tdc) gated ring oscillator (gro) pvt corners. analog data selector reversible decoder power supply. nano transistors carbon nanotube filed effect transistors power supply. 1. introduction autosar. genetic algorithm mmic doherty power amplifier phase shifter snr and low power. quasi-cyclic -low-density-parity-check (qc-ldpc) richardson and urbanke lower- triangular algorithm wlan (ieee802.11n) low pass filter. switched-capacitor finite impulse response (fir) parallel fir carry-look-ahead adder (cla) booth multiplier radix-2 fft radix-4 fft single path delay commutator pn (phase noise analy vco (voltage controlled oscillator) lpf (low pass filter) pd (phase detector) pll (phase locked loop) read/write assist circuitry standby start-up thermal hot spots kink energy level triggered flip-flop quantum-dot cellular automata (qca) counter nanometre scale. iterative dfg non-canonical. cutset retiming folding vlsi signal processing signal assessment transient noise assessment aural noise spectral exploration digital multiplier power and delay modified booth multiplier (mbe) high performance architecture unate function boolean decomposition rca verilog hdl. cia cla rf cmoslna wimax finite impulse response (fir) filter clock power datapath hdmi serial interface usb supply current gbps advanced verification methodology test bench. verification simulation software firefly algorithm transistor sizing low power vlsi circuit. binary compressor alu designing sctmr scan chains & sctmr. critical applications fault recovery tolerance firm ip core i2c protocols asic designing serial bus interfaces ip designing. on-chip communications field programming gate array (fpga) application specific integrated circuit (asic) reconfigurable dsp processor software defined radio (sdr) union of graph signal flow graph (sfg) digital signal processing (dsp) processor femtocells; handover; soft handover; hard handover lifting scheme (ls) filter bank (fb). modulo rns division residue number system (rns) integer wavelet transform (iwt) average latency deflection routing minimal buffering dac stuck_open stuck_short fpga (field programmable gate array). atm (automated teller machine) hdl (hardware description language) subthreshold slope (ss) impact ionization barrier tunneling schottky-contacts analog- to- digital converter successive approximation split array digital- to- analog converter charge redistribution benchmark circuit& noise iscas85 logic gate soft error android api ndef nfc class ab output stage row driver column driver liquid crystal display (lcd) gamma correction differential mux average power consumption analog signals. sub threshold multiplexer source coupled logic reversible decoder etc. low power circuit; carbon nanotube filed effect tr dg-pnin tfet tunnel field effect transistor (tfet) ion/ioff ratio dg-pin tfet psnr karatsuba ofman multiplier gaussian image filter mitchell log multiplier phase lock loop (pll) delay lock loop (dll) current balanced logic (cbl) current starved inverter (csi) source coupled logic (scl) comparator flash adc. variable switching voltage threshold inverter quantization drains circuit cascaded stages and source driver buffer circuits jldmsg (junctionless dual material surrounding gat short channel effects (sce). mrfb filter bank da based multiplication multipliers transistor stacking. 12 lead ecg test methodology ate automated test equipment dcl pin parametric unit variable-amplitude dithering digital calibration mtcmos inverter pocket dgtfet xrtl tasks/functions (xtf) emulator transactor interface (tif) universal verification component (uvc) verification ip (vip). testbench-xpress (tbx) systemverilog acceleratable uvc standard co-emulation api: modelling interface (sc field programmable gate arrays reverse converters chinese remainder theorem residue arithmetic and embedded block ram ieee754 standard floating point format look-up tables complex floating point arithmetic hardware on-chip ram processor hardware and embedded block ram ieee754 standard floating point format look-up tables complex floating point arithmetic hardware on-chip ram processor hardware matching networks s-parameters output power body-bia s. transmission gate gate diffusion input digital circuits leakage current . dual sub-threshold dpa resistance side channel attack risa clock- gati ng. interrupt risc reversible comparator signed ar ithmetic cade nce fpgas validation testbench asics power clock diode adiabatic logic circuits energy tri-state inverters boolean algebra clustering. 1. introduction karnaugh map digital logic circuit cascode topology 1. introduction rfic impedance matching power optimization recursive encoder/decoder bulk driven. static d flip-flop dual-edge triggered vedic multiplier. anurupye nikhilam navatashcaramam dashatah urdhva tiryagbhyam shannon’s expansion theorem carry propagate adder low power vlsi design. gate diffusion input technique flash analog to digital converter resistorless switched inverter scheme (sis) cmos 45nm read/write transitions area & power performance analysis zbt sram low drop-out low quiescent current voltage regulator lector technique. cmos buffer quiescent current class-ab rail-to-rail finite state machine; parking system; virtex- 5 arithmetic circuit logic circuit parity preserving gates fault tolerant full adder von neumann landauer limit reversible computing cell library bidirectional buffer shielding skewing rotation mode roc vectoring mode scale free cordic systolic array pipeline architecture. integrated circuit spatial wave-function switched fet digitalto- analog converter (dac) analog-to-digital converter (adc) power delay product (pdp). simulation.